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@@ -0,0 +1,1175 @@
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+/*
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+Copyright (c) 2023 tevador <tevador@gmail.com>
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+
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+All rights reserved.
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+
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+Redistribution and use in source and binary forms, with or without
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+modification, are permitted provided that the following conditions are met:
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+ * Redistributions of source code must retain the above copyright
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+ notice, this list of conditions and the following disclaimer.
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+ * Redistributions in binary form must reproduce the above copyright
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+ notice, this list of conditions and the following disclaimer in the
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+ documentation and/or other materials provided with the distribution.
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+ * Neither the name of the copyright holder nor the
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+ names of its contributors may be used to endorse or promote products
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+ derived from this software without specific prior written permission.
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+
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+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+*/
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+
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+#include <stdexcept>
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+#include <cstring>
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+#include <climits>
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+#include <cassert>
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+#include "jit_compiler_rv64.hpp"
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+#include "jit_compiler_rv64_static.hpp"
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+#include "superscalar.hpp"
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+#include "program.hpp"
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+#include "reciprocal.h"
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+#include "virtual_memory.h"
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+
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+
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+namespace {
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+#define HANDLER_ARGS randomx::CompilerState& state, randomx::Instruction isn, int i
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+ using InstructionHandler = void(HANDLER_ARGS);
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+ extern InstructionHandler* opcodeMap1[256];
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+}
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+
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+namespace rv64 {
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+ constexpr uint16_t C_LUI = 0x6001;
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+ constexpr uint32_t LUI = 0x00000037;
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+ constexpr uint16_t C_ADDI = 0x0001;
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+ constexpr uint32_t ADDI = 0x00000013;
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+ constexpr uint32_t ADDIW = 0x0000001b;
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+ constexpr uint16_t C_ADD = 0x9002;
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+ constexpr uint32_t ADD = 0x00000033;
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+ constexpr uint32_t SHXADD = 0x20000033; //Zba
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+ constexpr uint32_t SLL = 0x00001033;
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+ constexpr uint32_t SRL = 0x00005033;
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+ constexpr uint32_t SLLI = 0x00001013;
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+ constexpr uint32_t C_SLLI = 0x0002;
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+ constexpr uint32_t SRLI = 0x00005013;
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+ constexpr uint32_t AND = 0x00007033;
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+ constexpr uint32_t ANDI = 0x00007013;
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+ constexpr uint16_t C_AND = 0x8c61;
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+ constexpr uint16_t C_ANDI = 0x8801;
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+ constexpr uint32_t OR = 0x00006033;
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+ constexpr uint16_t C_OR = 0x8c41;
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+ constexpr uint32_t XOR = 0x00004033;
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+ constexpr uint16_t C_XOR = 0x8c21;
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+ constexpr uint32_t LD = 0x00003003;
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+ constexpr uint16_t C_LD = 0x6000;
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+ constexpr uint16_t C_LW = 0x4000;
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+ constexpr uint32_t SD = 0x00003023;
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+ constexpr uint32_t SUB = 0x40000033;
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+ constexpr uint16_t C_SUB = 0x8c01;
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+ constexpr uint32_t MUL = 0x02000033;
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+ constexpr uint32_t MULHU = 0x02003033;
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+ constexpr uint32_t MULH = 0x02001033;
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+ constexpr uint16_t C_MV = 0x8002;
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+ constexpr uint32_t ROR = 0x60005033; //Zbb
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+ constexpr uint32_t RORI = 0x60005013; //Zbb
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+ constexpr uint32_t ROL = 0x60001033; //Zbb
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+ constexpr uint32_t FMV_X_D = 0xe2000053;
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+ constexpr uint32_t FMV_D_X = 0xf2000053;
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+ constexpr uint32_t FMV_D = 0x22000053;
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+ constexpr uint32_t FADD_D = 0x02007053;
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+ constexpr uint32_t FSUB_D = 0x0a007053;
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+ constexpr uint32_t FMUL_D = 0x12007053;
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+ constexpr uint32_t FDIV_D = 0x1a007053;
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+ constexpr uint32_t FSQRT_D = 0x5a007053;
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+ constexpr uint32_t FCVT_D_W = 0xd2000053;
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+ constexpr uint32_t FSRM = 0x00201073;
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+ constexpr uint16_t C_BEQZ = 0xc001;
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+ constexpr uint32_t BEQ = 0x00000063;
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+ constexpr uint16_t C_BNEZ = 0xe001;
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+ constexpr uint32_t JAL = 0x0000006f;
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+ constexpr uint16_t C_RET = 0x8082;
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+}
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+
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+namespace randomx {
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+
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+ constexpr size_t MaxRandomXInstrCodeSize = 56; //FDIV_M requires 56 bytes of rv64 code
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+ constexpr size_t MaxSuperscalarInstrSize = 12; //IXOR_C requires 12 bytes of rv64 code
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+ constexpr size_t SuperscalarProgramHeader = 136; //overhead per superscalar program
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+ constexpr size_t CodeAlign = 4096; //align code size to a multiple of 4 KiB
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+ constexpr size_t LiteralPoolSize = CodeAlign;
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+ constexpr size_t SuperscalarLiteraPoolSize = RANDOMX_CACHE_ACCESSES * CodeAlign;
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+ constexpr size_t ReserveCodeSize = CodeAlign; //prologue, epilogue + reserve
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+
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+ constexpr size_t RandomXCodeSize = alignSize(LiteralPoolSize + ReserveCodeSize + MaxRandomXInstrCodeSize * RANDOMX_PROGRAM_SIZE, CodeAlign);
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+ constexpr size_t SuperscalarSize = alignSize(SuperscalarLiteraPoolSize + ReserveCodeSize + (SuperscalarProgramHeader + MaxSuperscalarInstrSize * SuperscalarMaxSize) * RANDOMX_CACHE_ACCESSES, CodeAlign);
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+
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+ static_assert(RandomXCodeSize < INT32_MAX / 2, "RandomXCodeSize is too large");
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+ static_assert(SuperscalarSize < INT32_MAX / 2, "SuperscalarSize is too large");
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+
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+ constexpr uint32_t CodeSize = RandomXCodeSize + SuperscalarSize;
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+ constexpr uint32_t ExecutableSize = CodeSize - LiteralPoolSize;
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+
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+ constexpr int32_t LiteralPoolOffset = LiteralPoolSize / 2;
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+ constexpr int32_t SuperScalarLiteralPoolOffset = RandomXCodeSize;
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+ constexpr int32_t SuperScalarLiteralPoolRefOffset = RandomXCodeSize + (RANDOMX_CACHE_ACCESSES - 1) * LiteralPoolSize + LiteralPoolOffset;
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+ constexpr int32_t SuperScalarHashOffset = SuperScalarLiteralPoolOffset + SuperscalarLiteraPoolSize;
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+
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+ constexpr int maskLog2(uint32_t x, int prev) {
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+ return x == 1 ? prev : maskLog2(x >> 1, prev + 1);
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+ }
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+
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+ constexpr int32_t unsigned32ToSigned2sCompl(uint32_t x) {
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+ return (-1 == ~0) ? (int32_t)x : (x > INT32_MAX ? (-(int32_t)(UINT32_MAX - x) - 1) : (int32_t)x);
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+ }
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+
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+ constexpr int MaskL1Shift = 32 - maskLog2(RANDOMX_SCRATCHPAD_L1, 0);
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+ constexpr int MaskL2Shift = 32 - maskLog2(RANDOMX_SCRATCHPAD_L2, 0);
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+ constexpr int MaskL3Shift = 32 - maskLog2(RANDOMX_SCRATCHPAD_L3, 0);
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+
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+ constexpr int RcpLiteralsOffset = 144;
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+
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+ constexpr int LiteralPoolReg = 3; //x3
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+ constexpr int SpadReg = 5; //x5
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+ constexpr int DataReg = 6; //x6
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+ constexpr int SuperscalarReg = 7; //x7
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+ constexpr int SshTmp1Reg = 28; //x28
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+ constexpr int SshTmp2Reg = 29; //x29
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+ constexpr int SshPoolReg = 30; //x30
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+ constexpr int SshRcpReg = 31; //x31
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+ constexpr int Tmp1Reg = 8; //x8
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+ constexpr int Tmp2Reg = 9; //x9
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+ constexpr int Tmp1RegF = 24; //f24
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+ constexpr int Tmp2RegF = 25; //f25
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+ constexpr int MaskL1Reg = 10; //x10
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+ constexpr int MaskL2Reg = 11; //x11
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+ constexpr int MaskFscalReg = 12; //x12
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+ constexpr int MaskEclear = 13; //x13
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+ constexpr int MaskEsetLo = 14; //x14
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+ constexpr int MaskEsetHi = 15; //x15
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+ constexpr int MaskL3Reg = 1; //x1
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+ constexpr int ReturnReg = 1; //x1
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+ constexpr int SpAddr0Reg = 26; //x26
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+ constexpr int OffsetXC = -8; //x8-x15
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+ constexpr int OffsetR = 16; //x16-x23
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+ constexpr int OffsetF = 0; //f0-f7
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+ constexpr int OffsetE = 8; //f8-f15
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+ constexpr int OffsetA = 16; //f16-f23
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+ constexpr int OffsetRcp = 28; //x28-x31
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+ constexpr int OffsetRcpF = 22; //f26-f31
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+ constexpr int OffsetSsh = 8; //x8-x15
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+
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+ //destination register (bit 7+)
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+ constexpr int rvrd(int reg) {
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+ return reg << 7;
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+ }
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+
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+ //first source register (bit 15+)
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+ constexpr int rvrs1(int reg) {
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+ return reg << 15;
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+ }
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+
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+ //second source register (bit 20+)
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+ constexpr int rvrs2(int reg) {
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+ return reg << 20;
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+ }
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+
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+ //compressed source register (bit 2+)
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+ constexpr int rvcrs(int reg) {
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+ return reg << 2;
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+ }
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+
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+ //base instruction: {op} x{rd}, x{rs1}, x{rs2}
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+ constexpr uint32_t rvi(uint32_t op, int rd, int rs1, int rs2 = 0) {
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+ return op | rvrs2(rs2) | rvrs1(rs1) | rvrd(rd);
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+ }
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+
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+ //compressed instruction: op x{rd}, x{rs}
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+ constexpr uint16_t rvc(uint16_t op, int rd, int rs) {
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+ return op | rvrd(rd) | rvcrs(rs);
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+ }
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+
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+ //compressed instruction: op x{rd}, imm6
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+ constexpr uint16_t rvc(uint16_t op, int imm5, int rd, int imm40) {
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+ return op | (imm5 << 12) | rvrd(rd) | (imm40 << 2);
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+ }
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+
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+ constexpr int regR(int reg) {
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+ return reg + OffsetR;
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+ }
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+
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+ constexpr int regLoA(int reg) {
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+ return 2 * reg + OffsetA;
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+ }
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+
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+ constexpr int regHiA(int reg) {
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+ return 2 * reg + OffsetA + 1;
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+ }
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+
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+ constexpr int regLoF(int reg) {
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+ return 2 * reg + OffsetF;
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+ }
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+
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+ constexpr int regHiF(int reg) {
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+ return 2 * reg + OffsetF + 1;
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+ }
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+
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+ constexpr int regLoE(int reg) {
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+ return 2 * reg + OffsetE;
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+ }
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+
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+ constexpr int regHiE(int reg) {
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+ return 2 * reg + OffsetE + 1;
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+ }
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+
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+ constexpr int regRcp(int reg) {
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+ return reg + OffsetRcp;
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+ }
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+
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+ constexpr int regRcpF(int reg) {
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+ return reg + OffsetRcpF;
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+ }
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+
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+ constexpr int regSS(int reg) {
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+ return reg + OffsetSsh;
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+ }
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+
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+ static const uint8_t* codeLiterals = (uint8_t*)&randomx_riscv64_literals;
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+ static const uint8_t* codeLiteralsEnd = (uint8_t*)&randomx_riscv64_literals_end;
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+ static const uint8_t* codeDataInit = (uint8_t*)&randomx_riscv64_data_init;
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+ static const uint8_t* codeFixDataCall = (uint8_t*)&randomx_riscv64_fix_data_call;
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+ static const uint8_t* codePrologue = (uint8_t*)&randomx_riscv64_prologue;
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+ static const uint8_t* codeLoopBegin = (uint8_t*)&randomx_riscv64_loop_begin;
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+ static const uint8_t* codeDataRead = (uint8_t*)&randomx_riscv64_data_read;
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+ static const uint8_t* codeDataReadLight = (uint8_t*)&randomx_riscv64_data_read_light;
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+ static const uint8_t* codeFixLoopCall = (uint8_t*)&randomx_riscv64_fix_loop_call;
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+ static const uint8_t* codeSpadStore = (uint8_t*)&randomx_riscv64_spad_store;
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+ static const uint8_t* codeSpadStoreHardAes = (uint8_t*)&randomx_riscv64_spad_store_hardaes;
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+ static const uint8_t* codeSpadStoreSoftAes = (uint8_t*)&randomx_riscv64_spad_store_softaes;
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+ static const uint8_t* codeLoopEnd = (uint8_t*)&randomx_riscv64_loop_end;
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+ static const uint8_t* codeFixContinueLoop = (uint8_t*)&randomx_riscv64_fix_continue_loop;
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+ static const uint8_t* codeEpilogue = (uint8_t*)&randomx_riscv64_epilogue;
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+ static const uint8_t* codeSoftAes = (uint8_t*)&randomx_riscv64_softaes;
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+ static const uint8_t* codeProgramEnd = (uint8_t*)&randomx_riscv64_program_end;
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+ static const uint8_t* codeSshInit = (uint8_t*)&randomx_riscv64_ssh_init;
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+ static const uint8_t* codeSshLoad = (uint8_t*)&randomx_riscv64_ssh_load;
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+ static const uint8_t* codeSshPrefetch = (uint8_t*)&randomx_riscv64_ssh_prefetch;
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+ static const uint8_t* codeSshEnd = (uint8_t*)&randomx_riscv64_ssh_end;
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+
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+ static const int32_t sizeLiterals = codeLiteralsEnd - codeLiterals;
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+ static const int32_t sizeDataInit = codePrologue - codeDataInit;
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+ static const int32_t sizePrologue = codeLoopBegin - codePrologue;
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+ static const int32_t sizeLoopBegin = codeDataRead - codeLoopBegin;
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+ static const int32_t sizeDataRead = codeDataReadLight - codeDataRead;
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+ static const int32_t sizeDataReadLight = codeSpadStore - codeDataReadLight;
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+ static const int32_t sizeSpadStore = codeSpadStoreHardAes - codeSpadStore;
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+ static const int32_t sizeSpadStoreSoftAes = codeLoopEnd - codeSpadStoreSoftAes;
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+ static const int32_t sizeLoopEnd = codeEpilogue - codeLoopEnd;
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+ static const int32_t sizeEpilogue = codeSoftAes - codeEpilogue;
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+ static const int32_t sizeSoftAes = codeProgramEnd - codeSoftAes;
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+ static const int32_t sizeSshInit = codeSshLoad - codeSshInit;
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+ static const int32_t sizeSshLoad = codeSshPrefetch - codeSshLoad;
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+ static const int32_t sizeSshPrefetch = codeSshEnd - codeSshPrefetch;
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+
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+ static const int32_t offsetFixDataCall = codeFixDataCall - codeDataInit;
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+ static const int32_t offsetFixLoopCall = codeFixLoopCall - codeDataReadLight;
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+ static const int32_t offsetFixContinueLoop = codeFixContinueLoop - codeLoopEnd;
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+
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+ static const int32_t LoopTopPos = LiteralPoolSize + sizeDataInit + sizePrologue;
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+ static const int32_t RandomXCodePos = LoopTopPos + sizeLoopBegin;
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+
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+ static void clearCache(CodeBuffer& buf) {
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+#ifdef __GNUC__
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+ __builtin___clear_cache((char*)buf.code, (char*)(buf.code + CodeSize));
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+#endif
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+ }
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+
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+ //emits code to calculate: x{dst} = x{src} + {imm32}
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+ //takes 1-3 isns, 2-10 bytes
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+ static void emitImm32(CodeBuffer& buf, int32_t imm, int dst, int src = 0, int tmp = 0) {
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+
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+ //lower 12 bits
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+ int32_t limm = (imm << 20) >> 20;
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+ //upper 20 bits
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+ int32_t uimm = (imm >> 12) + (limm < 0);
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+
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+ //If there are no upper bits, the whole thing
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+ //can be done with a single instruction.
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+ if (uimm == 0) {
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+ //addi x{dst}, x{src}, {limm}
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+ buf.emit(rvi(rv64::ADDI, dst, src, limm));
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+ return;
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+ }
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+
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+ //dst1 is the register where imm will be materialized
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+ int dst1 = src != dst ? dst : tmp;
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+ assert(dst1 != 0);
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+ //src1 is the register that will be added to the result
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+ int src1 = src != dst ? src : dst1;
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+
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+ //load upper bits
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+ if (uimm >= -32 && uimm <= 31) {
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+ //c.lui x{dst1}, {uimm}
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+ buf.emit(rvc(rv64::C_LUI, (uimm < 0), dst1, (uimm & 31)));
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+ }
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+ else {
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+ //lui x{dst1}, {uimm}
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+ buf.emit(rv64::LUI | (uimm << 12) | rvrd(dst1));
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+ }
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+ //load lower bits
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+ if (limm != 0) {
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+ //Note: this must be addiw NOT addi, otherwise the upper 32 bits
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+ //of the 64-bit register will be incorrect.
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+ //addiw x{dst1}, x{dst1}, {limm}
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+ buf.emit(rvi(rv64::ADDIW, dst1, dst1, limm));
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+ }
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+ //add src
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|
|
+ if (src1 != 0) {
|
|
|
+ //c.add x{dst}, x{src1}
|
|
|
+ buf.emit(rvc(rv64::C_ADD, dst, src1));
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ //x9 = &Scratchpad[isn.imm]
|
|
|
+ //takes 3 isns, 10 bytes
|
|
|
+ static void genAddressRegImm(CodeBuffer& buf, const Instruction& isn) {
|
|
|
+ //signed offset 8-byte aligned
|
|
|
+ int32_t imm = unsigned32ToSigned2sCompl(isn.getImm32()) & ScratchpadL3Mask;
|
|
|
+ //x9 = x5 + {imm}
|
|
|
+ emitImm32(buf, imm, Tmp2Reg, SpadReg, Tmp1Reg);
|
|
|
+ }
|
|
|
+
|
|
|
+ //x9 = &Scratchpad[isn.src + isn.imm] (for reading)
|
|
|
+ //takes 5 isns, 12 bytes
|
|
|
+ static void genAddressReg(CodeBuffer& buf, const Instruction& isn) {
|
|
|
+ int shift, maskReg;
|
|
|
+ if (isn.getModMem()) {
|
|
|
+ shift = MaskL1Shift;
|
|
|
+ maskReg = MaskL1Reg;
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ shift = MaskL2Shift;
|
|
|
+ maskReg = MaskL2Reg;
|
|
|
+ }
|
|
|
+ int32_t imm = unsigned32ToSigned2sCompl(isn.getImm32());
|
|
|
+ imm = (imm << shift) >> shift;
|
|
|
+ //x9 = x{src} + {imm}
|
|
|
+ emitImm32(buf, imm, Tmp2Reg, regR(isn.src), Tmp1Reg);
|
|
|
+ //c.and x9, x{maskReg}
|
|
|
+ buf.emit(rvc(rv64::C_AND, (Tmp2Reg + OffsetXC), (maskReg + OffsetXC)));
|
|
|
+ //c.add x9, x{spadReg}
|
|
|
+ buf.emit(rvc(rv64::C_ADD, Tmp2Reg, SpadReg));
|
|
|
+ }
|
|
|
+
|
|
|
+ //x8 = Scratchpad[isn]
|
|
|
+ static void loadFromScratchpad(CodeBuffer& buf, const Instruction& isn) {
|
|
|
+ if (isn.src != isn.dst) {
|
|
|
+ //x9 = &Scratchpad[isn.src + isn.imm]
|
|
|
+ genAddressReg(buf, isn);
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ ///x9 = &Scratchpad[isn.imm]
|
|
|
+ genAddressRegImm(buf, isn);
|
|
|
+ }
|
|
|
+ //c.ld x8, 0(x9)
|
|
|
+ buf.emit(rvc(rv64::C_LD, Tmp2Reg + OffsetXC, Tmp1Reg + OffsetXC));
|
|
|
+ }
|
|
|
+
|
|
|
+ //x9 = &Scratchpad[isn.dst + isn.imm32] (for writing)
|
|
|
+ //takes 5 isns, 12-16 bytes
|
|
|
+ static void genAddressRegDst(CodeBuffer& buf, const Instruction& isn) {
|
|
|
+ if (isn.getModCond() < StoreL3Condition) {
|
|
|
+ int shift, maskReg;
|
|
|
+ if (isn.getModMem()) {
|
|
|
+ shift = MaskL1Shift;
|
|
|
+ maskReg = MaskL1Reg;
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ shift = MaskL2Shift;
|
|
|
+ maskReg = MaskL2Reg;
|
|
|
+ }
|
|
|
+ int32_t imm = unsigned32ToSigned2sCompl(isn.getImm32());
|
|
|
+ imm = (imm << shift) >> shift;
|
|
|
+ //x9 = x{dst} + {imm}
|
|
|
+ emitImm32(buf, imm, Tmp2Reg, regR(isn.dst), Tmp1Reg);
|
|
|
+ //c.and x9, x{maskReg}
|
|
|
+ buf.emit(rvc(rv64::C_AND, Tmp2Reg + OffsetXC, maskReg + OffsetXC));
|
|
|
+ //c.add x9, x5
|
|
|
+ buf.emit(rvc(rv64::C_ADD, Tmp2Reg, SpadReg));
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ int shift = MaskL3Shift;
|
|
|
+ int32_t imm = unsigned32ToSigned2sCompl(isn.getImm32());
|
|
|
+ imm = (imm << shift) >> shift;
|
|
|
+ //x9 = x{dst} + {imm}
|
|
|
+ emitImm32(buf, imm, Tmp2Reg, regR(isn.dst), Tmp1Reg);
|
|
|
+ //and x9, x9, x1
|
|
|
+ buf.emit(rvi(rv64::AND, Tmp2Reg, Tmp2Reg, MaskL3Reg));
|
|
|
+ //c.add x9, x5
|
|
|
+ buf.emit(rvc(rv64::C_ADD, Tmp2Reg, SpadReg));
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ static void emitRcpLiteral1(CodeBuffer& buf, uint64_t literal) {
|
|
|
+ //first 238 at positive offsets
|
|
|
+ if (buf.rcpCount < 238) {
|
|
|
+ buf.emitAt(LiteralPoolOffset + RcpLiteralsOffset + buf.rcpCount * 8, literal);
|
|
|
+ buf.rcpCount++;
|
|
|
+ }
|
|
|
+ //next 256 at negative offsets
|
|
|
+ else if (buf.rcpCount < 494) {
|
|
|
+ buf.emitAt(buf.rcpCount * 8 - (2048 - RcpLiteralsOffset), literal);
|
|
|
+ buf.rcpCount++;
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ //checked at compile time, but double-check here
|
|
|
+ throw std::runtime_error("Literal pool overflow");
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ static void emitRcpLiteral2(CodeBuffer& buf, uint64_t literal, int32_t numLiterals) {
|
|
|
+ //store the current literal in the pool
|
|
|
+ int32_t offset = 2040 - buf.rcpCount * 8;
|
|
|
+ buf.emitAt(SuperScalarLiteralPoolRefOffset + offset, literal);
|
|
|
+ buf.rcpCount++;
|
|
|
+ if (buf.rcpCount >= numLiterals) {
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ //load the next literal
|
|
|
+ offset -= 8;
|
|
|
+ int32_t imm = offset & 0xfff;
|
|
|
+ //ld x31, {offset}(x30)
|
|
|
+ buf.emit(rvi(rv64::LD, SshRcpReg, SshPoolReg, imm));
|
|
|
+ if (imm == 0x800) {
|
|
|
+ //move pool pointer back 4KB
|
|
|
+ //c.lui x29, 0xfffff
|
|
|
+ buf.emit(rvc(rv64::C_LUI, 1, SshTmp2Reg, 31));
|
|
|
+ //c.add x30, x29
|
|
|
+ buf.emit(rvc(rv64::C_ADD, SshPoolReg, SshTmp2Reg));
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ static void emitJump(CodeBuffer& buf, int dst, int32_t codePos, int32_t targetPos) {
|
|
|
+ int32_t imm = targetPos - codePos;
|
|
|
+ int32_t imm20 = (imm < 0) << 11;
|
|
|
+ int32_t imm1912 = (imm >> 7) & 8160;
|
|
|
+ int32_t imm11 = (imm >> 11) & 1;
|
|
|
+ int32_t imm101 = imm & 2046;
|
|
|
+ //jal x{dst}, {imm}
|
|
|
+ buf.emitAt(codePos, rvi(rv64::JAL, dst + imm1912, 0, imm20 + imm101 + imm11));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void emitInstruction(CompilerState& state, Instruction isn, int i) {
|
|
|
+ state.instructionOffsets[i] = state.codePos;
|
|
|
+ opcodeMap1[isn.opcode](state, isn, i);
|
|
|
+ }
|
|
|
+
|
|
|
+ static void emitProgramPrefix(CompilerState& state, Program& prog, ProgramConfiguration& pcfg) {
|
|
|
+ state.codePos = RandomXCodePos;
|
|
|
+ state.rcpCount = 0;
|
|
|
+ state.emitAt(LiteralPoolOffset + sizeLiterals, pcfg.eMask[0]);
|
|
|
+ state.emitAt(LiteralPoolOffset + sizeLiterals + 8, pcfg.eMask[1]);
|
|
|
+ for (unsigned i = 0; i < RegistersCount; ++i) {
|
|
|
+ state.registerUsage[i] = -1;
|
|
|
+ }
|
|
|
+ for (unsigned i = 0; i < prog.getSize(); ++i) {
|
|
|
+ Instruction instr = prog(i);
|
|
|
+ instr.src %= RegistersCount;
|
|
|
+ instr.dst %= RegistersCount;
|
|
|
+ emitInstruction(state, instr, i);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ static void emitProgramSuffix(CompilerState& state, ProgramConfiguration& pcfg) {
|
|
|
+ state.emit(codeSpadStore, sizeSpadStore);
|
|
|
+ int32_t fixPos = state.codePos;
|
|
|
+ state.emit(codeLoopEnd, sizeLoopEnd);
|
|
|
+ //xor x26, x{readReg0}, x{readReg1}
|
|
|
+ state.emitAt(fixPos, rvi(rv64::XOR, SpAddr0Reg, regR(pcfg.readReg0), regR(pcfg.readReg1)));
|
|
|
+ fixPos += offsetFixContinueLoop;
|
|
|
+ //j LoopTop
|
|
|
+ emitJump(state, 0, fixPos, LoopTopPos);
|
|
|
+ state.emit(codeEpilogue, sizeEpilogue);
|
|
|
+ }
|
|
|
+
|
|
|
+ static void generateSuperscalarCode(CodeBuffer& buf, Instruction isn, const std::vector<uint64_t>& reciprocalCache) {
|
|
|
+ switch ((SuperscalarInstructionType)isn.opcode)
|
|
|
+ {
|
|
|
+ case randomx::SuperscalarInstructionType::ISUB_R:
|
|
|
+ //c.sub x{dst}, x{src}
|
|
|
+ buf.emit(rvc(rv64::C_SUB, regSS(isn.dst) + OffsetXC, regSS(isn.src) + OffsetXC));
|
|
|
+ break;
|
|
|
+ case randomx::SuperscalarInstructionType::IXOR_R:
|
|
|
+ //c.xor x{dst}, x{src}
|
|
|
+ buf.emit(rvc(rv64::C_XOR, regSS(isn.dst) + OffsetXC, regSS(isn.src) + OffsetXC));
|
|
|
+ break;
|
|
|
+ case randomx::SuperscalarInstructionType::IADD_RS:
|
|
|
+ {
|
|
|
+ int shift = isn.getModShift();
|
|
|
+ if (shift == 0) {
|
|
|
+ //c.add x{dst}, x{src}
|
|
|
+ buf.emit(rvc(rv64::C_ADD, regSS(isn.dst), regSS(isn.src)));
|
|
|
+ }
|
|
|
+ else {
|
|
|
+#ifdef __riscv_zba
|
|
|
+ //sh{1,2,3}add x{dst}, x{src}, x{dst}
|
|
|
+ buf.emit(rv64::SHXADD | rvrs2(regSS(isn.dst)) | rvrs1(regSS(isn.src)) | (shift << 13) | rvrd(regSS(isn.dst)));
|
|
|
+#else
|
|
|
+ //slli x28, x{src}, {shift}
|
|
|
+ buf.emit(rvi(rv64::SLLI, SshTmp1Reg, regSS(isn.src), shift));
|
|
|
+ //c.add x{dst}, x28
|
|
|
+ buf.emit(rvc(rv64::C_ADD, regSS(isn.dst), SshTmp1Reg));
|
|
|
+#endif
|
|
|
+ }
|
|
|
+ }
|
|
|
+ break;
|
|
|
+ case randomx::SuperscalarInstructionType::IMUL_R:
|
|
|
+ //mul x{dst}, x{dst}, x{src}
|
|
|
+ buf.emit(rvi(rv64::MUL, regSS(isn.dst), regSS(isn.dst), regSS(isn.src)));
|
|
|
+ break;
|
|
|
+ case randomx::SuperscalarInstructionType::IROR_C:
|
|
|
+ {
|
|
|
+#ifdef __riscv_zbb
|
|
|
+ int32_t imm = isn.getImm32() & 63;
|
|
|
+ //rori x{dst}, x{dst}, {imm}
|
|
|
+ buf.emit(rvi(rv64::RORI, regSS(isn.dst), regSS(isn.dst), imm));
|
|
|
+#else
|
|
|
+ int32_t immr = isn.getImm32() & 63;
|
|
|
+ int32_t imml = -immr & 63;
|
|
|
+ int32_t imml5 = imml >> 5;
|
|
|
+ int32_t imml40 = imml & 31;
|
|
|
+ //srli x28, x{dst}, {immr}
|
|
|
+ buf.emit(rvi(rv64::SRLI, SshTmp1Reg, regSS(isn.dst), immr));
|
|
|
+ //c.slli x{dst}, {imml}
|
|
|
+ buf.emit(rvc(rv64::C_SLLI, imml5, regSS(isn.dst), imml40));
|
|
|
+ //or x{dst}, x{dst}, x28
|
|
|
+ buf.emit(rvi(rv64::OR, regSS(isn.dst), regSS(isn.dst), SshTmp1Reg));
|
|
|
+#endif
|
|
|
+ }
|
|
|
+ break;
|
|
|
+ case randomx::SuperscalarInstructionType::IADD_C7:
|
|
|
+ case randomx::SuperscalarInstructionType::IADD_C8:
|
|
|
+ case randomx::SuperscalarInstructionType::IADD_C9:
|
|
|
+ {
|
|
|
+ int32_t imm = unsigned32ToSigned2sCompl(isn.getImm32());
|
|
|
+ //x{dst} = x{dst} + {imm}
|
|
|
+ emitImm32(buf, imm, regSS(isn.dst), regSS(isn.dst), SshTmp1Reg);
|
|
|
+ }
|
|
|
+ break;
|
|
|
+ case randomx::SuperscalarInstructionType::IXOR_C7:
|
|
|
+ case randomx::SuperscalarInstructionType::IXOR_C8:
|
|
|
+ case randomx::SuperscalarInstructionType::IXOR_C9:
|
|
|
+ {
|
|
|
+ int32_t imm = unsigned32ToSigned2sCompl(isn.getImm32());
|
|
|
+ //x28 = {imm}
|
|
|
+ emitImm32(buf, imm, SshTmp1Reg);
|
|
|
+ //xor x{dst}, x{dst}, x28
|
|
|
+ buf.emit(rvi(rv64::XOR, regSS(isn.dst), regSS(isn.dst), SshTmp1Reg));
|
|
|
+ }
|
|
|
+ break;
|
|
|
+ case randomx::SuperscalarInstructionType::IMULH_R:
|
|
|
+ //mulhu x{dst}, x{dst}, x{src}
|
|
|
+ buf.emit(rvi(rv64::MULHU, regSS(isn.dst), regSS(isn.dst), regSS(isn.src)));
|
|
|
+ break;
|
|
|
+ case randomx::SuperscalarInstructionType::ISMULH_R:
|
|
|
+ //mulh x{dst}, x{dst}, x{src}
|
|
|
+ buf.emit(rvi(rv64::MULH, regSS(isn.dst), regSS(isn.dst), regSS(isn.src)));
|
|
|
+ break;
|
|
|
+ case randomx::SuperscalarInstructionType::IMUL_RCP:
|
|
|
+ //mul x{dst}, x{dst}, x31
|
|
|
+ buf.emit(rvi(rv64::MUL, regSS(isn.dst), regSS(isn.dst), SshRcpReg));
|
|
|
+ //load the next literal into x31
|
|
|
+ emitRcpLiteral2(buf, reciprocalCache[isn.getImm32()], reciprocalCache.size());
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ UNREACHABLE;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ size_t JitCompilerRV64::getCodeSize() {
|
|
|
+ return CodeSize;
|
|
|
+ }
|
|
|
+
|
|
|
+ JitCompilerRV64::JitCompilerRV64() {
|
|
|
+ state.code = (uint8_t*)allocMemoryPages(CodeSize);
|
|
|
+ if (state.code == nullptr)
|
|
|
+ throw std::runtime_error("allocMemoryPages");
|
|
|
+ state.emitAt(LiteralPoolOffset, codeLiterals, sizeLiterals);
|
|
|
+ state.emitAt(LiteralPoolSize, codeDataInit, sizeDataInit + sizePrologue + sizeLoopBegin);
|
|
|
+ entryDataInit = state.code + LiteralPoolSize;
|
|
|
+ entryProgram = state.code + LiteralPoolSize + sizeDataInit;
|
|
|
+ //jal x1, SuperscalarHash
|
|
|
+ emitJump(state, ReturnReg, LiteralPoolSize + offsetFixDataCall, SuperScalarHashOffset);
|
|
|
+ }
|
|
|
+
|
|
|
+ JitCompilerRV64::~JitCompilerRV64() {
|
|
|
+ freePagedMemory(state.code, CodeSize);
|
|
|
+ }
|
|
|
+
|
|
|
+ void JitCompilerRV64::enableAll() {
|
|
|
+ setPagesRWX(entryDataInit, ExecutableSize);
|
|
|
+ }
|
|
|
+
|
|
|
+ void JitCompilerRV64::enableWriting() {
|
|
|
+ setPagesRW(entryDataInit, ExecutableSize);
|
|
|
+ }
|
|
|
+
|
|
|
+ void JitCompilerRV64::enableExecution() {
|
|
|
+ setPagesRX(entryDataInit, ExecutableSize);
|
|
|
+ }
|
|
|
+
|
|
|
+ void JitCompilerRV64::generateProgram(Program& prog, ProgramConfiguration& pcfg) {
|
|
|
+ emitProgramPrefix(state, prog, pcfg);
|
|
|
+ int32_t fixPos = state.codePos;
|
|
|
+ state.emit(codeDataRead, sizeDataRead);
|
|
|
+ //xor x8, x{readReg2}, x{readReg3}
|
|
|
+ state.emitAt(fixPos, rvi(rv64::XOR, Tmp1Reg, regR(pcfg.readReg2), regR(pcfg.readReg3)));
|
|
|
+ emitProgramSuffix(state, pcfg);
|
|
|
+ clearCache(state);
|
|
|
+ }
|
|
|
+
|
|
|
+ void JitCompilerRV64::generateProgramLight(Program& prog, ProgramConfiguration& pcfg, uint32_t datasetOffset) {
|
|
|
+ emitProgramPrefix(state, prog, pcfg);
|
|
|
+ int32_t fixPos = state.codePos;
|
|
|
+ state.emit(codeDataReadLight, sizeDataReadLight);
|
|
|
+ //xor x8, x{readReg2}, x{readReg3}
|
|
|
+ state.emitAt(fixPos, rvi(rv64::XOR, Tmp1Reg, regR(pcfg.readReg2), regR(pcfg.readReg3)));
|
|
|
+ int32_t imm = datasetOffset / CacheLineSize;
|
|
|
+ int32_t limm = (imm << 20) >> 20;
|
|
|
+ int32_t uimm = (imm >> 12) + (limm < 0);
|
|
|
+ //lui x9, {uimm}
|
|
|
+ state.emitAt(fixPos + 4, rv64::LUI | (uimm << 12) | rvrd(Tmp2Reg));
|
|
|
+ //addi x9, x9, {limm}
|
|
|
+ state.emitAt(fixPos + 8, rvi(rv64::ADDI, Tmp2Reg, Tmp2Reg, limm));
|
|
|
+ fixPos += offsetFixLoopCall;
|
|
|
+ //jal x1, SuperscalarHash
|
|
|
+ emitJump(state, ReturnReg, fixPos, SuperScalarHashOffset);
|
|
|
+ emitProgramSuffix(state, pcfg);
|
|
|
+ clearCache(state);
|
|
|
+ }
|
|
|
+
|
|
|
+ void JitCompilerRV64::generateSuperscalarHash(SuperscalarProgram programs[RANDOMX_CACHE_ACCESSES], std::vector<uint64_t>& reciprocalCache) {
|
|
|
+ state.codePos = SuperScalarHashOffset;
|
|
|
+ state.rcpCount = 0;
|
|
|
+ state.emit(codeSshInit, sizeSshInit);
|
|
|
+ for (unsigned j = 0; j < RANDOMX_CACHE_ACCESSES; ++j) {
|
|
|
+ SuperscalarProgram& prog = programs[j];
|
|
|
+ for (unsigned i = 0; i < prog.getSize(); ++i) {
|
|
|
+ Instruction instr = prog(i);
|
|
|
+ generateSuperscalarCode(state, instr, reciprocalCache);
|
|
|
+ }
|
|
|
+ state.emit(codeSshLoad, sizeSshLoad);
|
|
|
+ if (j < RANDOMX_CACHE_ACCESSES - 1) {
|
|
|
+ int32_t fixPos = state.codePos;
|
|
|
+ state.emit(codeSshPrefetch, sizeSshPrefetch);
|
|
|
+ //and x7, x{addrReg}, x7
|
|
|
+ state.emitAt(fixPos, rvi(rv64::AND, SuperscalarReg, regSS(prog.getAddressRegister()), SuperscalarReg));
|
|
|
+ }
|
|
|
+ }
|
|
|
+ state.emit(rvc(rv64::C_RET, 0, 0));
|
|
|
+ clearCache(state);
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_IADD_RS(HANDLER_ARGS) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+ int shift = isn.getModShift();
|
|
|
+ if (shift == 0) {
|
|
|
+ //c.add x{dst}, x{src}
|
|
|
+ state.emit(rvc(rv64::C_ADD, regR(isn.dst), regR(isn.src)));
|
|
|
+ }
|
|
|
+ else {
|
|
|
+#ifdef __riscv_zba
|
|
|
+ //sh{1,2,3}add x{dst}, x{src}, x{dst}
|
|
|
+ state.emit(rv64::SHXADD | rvrs2(regR(isn.dst)) | rvrs1(regR(isn.src)) | (shift << 13) | rvrd(regR(isn.dst)));
|
|
|
+#else
|
|
|
+ //slli x8, x{src}, {shift}
|
|
|
+ state.emit(rvi(rv64::SLLI, Tmp1Reg, regR(isn.src), shift));
|
|
|
+ //c.add x{dst}, x8
|
|
|
+ state.emit(rvc(rv64::C_ADD, regR(isn.dst), Tmp1Reg));
|
|
|
+#endif
|
|
|
+ }
|
|
|
+ if (isn.dst == RegisterNeedsDisplacement) {
|
|
|
+ int32_t imm = unsigned32ToSigned2sCompl(isn.getImm32());
|
|
|
+ //x{dst} = x{dst} + {imm}
|
|
|
+ emitImm32(state, imm, regR(isn.dst), regR(isn.dst), Tmp1Reg);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_IADD_M(HANDLER_ARGS) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+ loadFromScratchpad(state, isn);
|
|
|
+ //c.add x{dst}, x8
|
|
|
+ state.emit(rvc(rv64::C_ADD, regR(isn.dst), Tmp1Reg));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_ISUB_R(HANDLER_ARGS) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+ if (isn.src != isn.dst) {
|
|
|
+ //sub x{dst}, x{dst}, x{src}
|
|
|
+ state.emit(rvi(rv64::SUB, regR(isn.dst), regR(isn.dst), regR(isn.src)));
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ int32_t imm = unsigned32ToSigned2sCompl(-isn.getImm32()); //convert to add
|
|
|
+ //x{dst} = x{dst} + {-imm}
|
|
|
+ emitImm32(state, imm, regR(isn.dst), regR(isn.dst), Tmp1Reg);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_ISUB_M(HANDLER_ARGS) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+ loadFromScratchpad(state, isn);
|
|
|
+ //sub x{dst}, x{dst}, x8
|
|
|
+ state.emit(rvi(rv64::SUB, regR(isn.dst), regR(isn.dst), Tmp1Reg));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_IMUL_R(HANDLER_ARGS) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+ if (isn.src != isn.dst) {
|
|
|
+ //mul x{dst}, x{dst}, x{src}
|
|
|
+ state.emit(rvi(rv64::MUL, regR(isn.dst), regR(isn.dst), regR(isn.src)));
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ int32_t imm = unsigned32ToSigned2sCompl(isn.getImm32());
|
|
|
+ //x8 = {imm}
|
|
|
+ emitImm32(state, imm, Tmp1Reg);
|
|
|
+ //mul x{dst}, x{dst}, x8
|
|
|
+ state.emit(rvi(rv64::MUL, regR(isn.dst), regR(isn.dst), Tmp1Reg));
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_IMUL_M(HANDLER_ARGS) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+ loadFromScratchpad(state, isn);
|
|
|
+ //mul x{dst}, x{dst}, x8
|
|
|
+ state.emit(rvi(rv64::MUL, regR(isn.dst), regR(isn.dst), Tmp1Reg));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_IMULH_R(HANDLER_ARGS) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+ //mulhu x{dst}, x{dst}, x{src}
|
|
|
+ state.emit(rvi(rv64::MULHU, regR(isn.dst), regR(isn.dst), regR(isn.src)));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_IMULH_M(HANDLER_ARGS) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+ loadFromScratchpad(state, isn);
|
|
|
+ //mulhu x{dst}, x{dst}, x8
|
|
|
+ state.emit(rvi(rv64::MULHU, regR(isn.dst), regR(isn.dst), Tmp1Reg));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_ISMULH_R(HANDLER_ARGS) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+ //mulh x{dst}, x{dst}, x{src}
|
|
|
+ state.emit(rvi(rv64::MULH, regR(isn.dst), regR(isn.dst), regR(isn.src)));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_ISMULH_M(HANDLER_ARGS) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+ loadFromScratchpad(state, isn);
|
|
|
+ //mulh x{dst}, x{dst}, x8
|
|
|
+ state.emit(rvi(rv64::MULH, regR(isn.dst), regR(isn.dst), Tmp1Reg));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_IMUL_RCP(HANDLER_ARGS) {
|
|
|
+ uint64_t divisor = isn.getImm32();
|
|
|
+ if (!isZeroOrPowerOf2(divisor)) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+ if (state.rcpCount < 4) {
|
|
|
+ //mul x{dst}, x{dst}, x{rcp}
|
|
|
+ state.emit(rvi(rv64::MUL, regR(isn.dst), regR(isn.dst), regRcp(state.rcpCount)));
|
|
|
+ }
|
|
|
+ else if (state.rcpCount < 10) {
|
|
|
+ //fmv.x.d x8, f{rcp}
|
|
|
+ state.emit(rvi(rv64::FMV_X_D, Tmp1Reg, regRcpF(state.rcpCount)));
|
|
|
+ //mul x{dst}, x{dst}, x8
|
|
|
+ state.emit(rvi(rv64::MUL, regR(isn.dst), regR(isn.dst), Tmp1Reg));
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ int32_t offset = RcpLiteralsOffset + state.rcpCount * 8;
|
|
|
+ //ld x8, {offset}(x3)
|
|
|
+ state.emit(rvi(rv64::LD, Tmp1Reg, LiteralPoolReg, offset));
|
|
|
+ //mul x{dst}, x{dst}, x8
|
|
|
+ state.emit(rvi(rv64::MUL, regR(isn.dst), regR(isn.dst), Tmp1Reg));
|
|
|
+ }
|
|
|
+ emitRcpLiteral1(state, randomx_reciprocal_fast(divisor));
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_INEG_R(HANDLER_ARGS) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+ //sub x{dst}, x0, x{dst}
|
|
|
+ state.emit(rvi(rv64::SUB, regR(isn.dst), 0, regR(isn.dst)));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_IXOR_R(HANDLER_ARGS) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+ if (isn.src != isn.dst) {
|
|
|
+ //xor x{dst}, x{dst}, x{src}
|
|
|
+ state.emit(rvi(rv64::XOR, regR(isn.dst), regR(isn.dst), regR(isn.src)));
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ int32_t imm = unsigned32ToSigned2sCompl(isn.getImm32());
|
|
|
+ //x8 = {imm}
|
|
|
+ emitImm32(state, imm, Tmp1Reg);
|
|
|
+ //xor x{dst}, x{dst}, x8
|
|
|
+ state.emit(rvi(rv64::XOR, regR(isn.dst), regR(isn.dst), Tmp1Reg));
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_IXOR_M(HANDLER_ARGS) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+ loadFromScratchpad(state, isn);
|
|
|
+ //xor x{dst}, x{dst}, x8
|
|
|
+ state.emit(rvi(rv64::XOR, regR(isn.dst), regR(isn.dst), Tmp1Reg));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_IROR_R(HANDLER_ARGS) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+#ifdef __riscv_zbb
|
|
|
+ if (isn.src != isn.dst) {
|
|
|
+ //ror x{dst}, x{dst}, x{src}
|
|
|
+ state.emit(rvi(rv64::ROR, regR(isn.dst), regR(isn.dst), regR(isn.src)));
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ int32_t imm = isn.getImm32() & 63;
|
|
|
+ //rori x{dst}, x{dst}, {imm}
|
|
|
+ state.emit(rvi(rv64::RORI, regR(isn.dst), regR(isn.dst), imm));
|
|
|
+ }
|
|
|
+#else
|
|
|
+ if (isn.src != isn.dst) {
|
|
|
+ //sub x8, x0, x{src}
|
|
|
+ state.emit(rvi(rv64::SUB, Tmp1Reg, 0, regR(isn.src)));
|
|
|
+ //srl x9, x{dst}, x{src}
|
|
|
+ state.emit(rvi(rv64::SRL, Tmp2Reg, regR(isn.dst), regR(isn.src)));
|
|
|
+ //sll x{dst}, x{dst}, x8
|
|
|
+ state.emit(rvi(rv64::SLL, regR(isn.dst), regR(isn.dst), Tmp1Reg));
|
|
|
+ //or x{dst}, x{dst}, x9
|
|
|
+ state.emit(rvi(rv64::OR, regR(isn.dst), regR(isn.dst), Tmp2Reg));
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ int32_t immr = isn.getImm32() & 63;
|
|
|
+ int32_t imml = -immr & 63;
|
|
|
+ int32_t imml5 = imml >> 5;
|
|
|
+ int32_t imml40 = imml & 31;
|
|
|
+ //srli x8, x{dst}, {immr}
|
|
|
+ state.emit(rvi(rv64::SRLI, Tmp1Reg, regR(isn.dst), immr));
|
|
|
+ //c.slli x{dst}, {imml}
|
|
|
+ state.emit(rvc(rv64::C_SLLI, imml5, regR(isn.dst), imml40));
|
|
|
+ //or x{dst}, x{dst}, x8
|
|
|
+ state.emit(rvi(rv64::OR, regR(isn.dst), regR(isn.dst), Tmp1Reg));
|
|
|
+ }
|
|
|
+#endif
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_IROL_R(HANDLER_ARGS) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+#ifdef __riscv_zbb
|
|
|
+ if (isn.src != isn.dst) {
|
|
|
+ //rol x{dst}, x{dst}, x{src}
|
|
|
+ state.emit(rvi(rv64::ROL, regR(isn.dst), regR(isn.dst), regR(isn.src)));
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ int32_t imm = -isn.getImm32() & 63;
|
|
|
+ //rori x{dst}, x{dst}, {imm}
|
|
|
+ state.emit(rvi(rv64::RORI, regR(isn.dst), regR(isn.dst), imm));
|
|
|
+ }
|
|
|
+#else
|
|
|
+ if (isn.src != isn.dst) {
|
|
|
+ //sub x8, x0, x{src}
|
|
|
+ state.emit(rvi(rv64::SUB, Tmp1Reg, 0, regR(isn.src)));
|
|
|
+ //sll x9, x{dst}, x{src}
|
|
|
+ state.emit(rvi(rv64::SLL, Tmp2Reg, regR(isn.dst), regR(isn.src)));
|
|
|
+ //srl x{dst}, x{dst}, x8
|
|
|
+ state.emit(rvi(rv64::SRL, regR(isn.dst), regR(isn.dst), Tmp1Reg));
|
|
|
+ //or x{dst}, x{dst}, x9
|
|
|
+ state.emit(rvi(rv64::OR, regR(isn.dst), regR(isn.dst), Tmp2Reg));
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ int32_t imml = isn.getImm32() & 63;
|
|
|
+ int32_t immr = -imml & 63;
|
|
|
+ int32_t imml5 = imml >> 5;
|
|
|
+ int32_t imml40 = imml & 31;
|
|
|
+ //srli x8, x{dst}, {immr}
|
|
|
+ state.emit(rvi(rv64::SRLI, Tmp1Reg, regR(isn.dst), immr));
|
|
|
+ //c.slli x{dst}, {imml}
|
|
|
+ state.emit(rvc(rv64::C_SLLI, imml5, regR(isn.dst), imml40));
|
|
|
+ //or x{dst}, x{dst}, x8
|
|
|
+ state.emit(rvi(rv64::OR, regR(isn.dst), regR(isn.dst), Tmp1Reg));
|
|
|
+ }
|
|
|
+#endif
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_ISWAP_R(HANDLER_ARGS) {
|
|
|
+ if (isn.src != isn.dst) {
|
|
|
+ state.registerUsage[isn.dst] = i;
|
|
|
+ state.registerUsage[isn.src] = i;
|
|
|
+ //c.mv x8, x{dst}
|
|
|
+ state.emit(rvc(rv64::C_MV, Tmp1Reg, regR(isn.dst)));
|
|
|
+ //c.mv x{dst}, x{src}
|
|
|
+ state.emit(rvc(rv64::C_MV, regR(isn.dst), regR(isn.src)));
|
|
|
+ //c.mv x{src}, x8
|
|
|
+ state.emit(rvc(rv64::C_MV, regR(isn.src), Tmp1Reg));
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_FSWAP_R(HANDLER_ARGS) {
|
|
|
+ //fmv.d f24, f{dst_lo}
|
|
|
+ state.emit(rvi(rv64::FMV_D, Tmp1RegF, regLoF(isn.dst), regLoF(isn.dst)));
|
|
|
+ //fmv.d f{dst_lo}, f{dst_hi}
|
|
|
+ state.emit(rvi(rv64::FMV_D, regLoF(isn.dst), regHiF(isn.dst), regHiF(isn.dst)));
|
|
|
+ //fmv.d f{dst_hi}, f24
|
|
|
+ state.emit(rvi(rv64::FMV_D, regHiF(isn.dst), Tmp1RegF, Tmp1RegF));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_FADD_R(HANDLER_ARGS) {
|
|
|
+ isn.dst %= RegisterCountFlt;
|
|
|
+ isn.src %= RegisterCountFlt;
|
|
|
+ //fadd.d f{dst_lo}, f{dst_lo}, f{src_lo}
|
|
|
+ state.emit(rvi(rv64::FADD_D, regLoF(isn.dst), regLoF(isn.dst), regLoA(isn.src)));
|
|
|
+ //fadd.d f{dst_hi}, f{dst_hi}, f{src_hi}
|
|
|
+ state.emit(rvi(rv64::FADD_D, regHiF(isn.dst), regHiF(isn.dst), regHiA(isn.src)));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_FADD_M(HANDLER_ARGS) {
|
|
|
+ isn.dst %= RegisterCountFlt;
|
|
|
+ //x9 = mem
|
|
|
+ genAddressReg(state, isn);
|
|
|
+ //lw x8, 0(x9)
|
|
|
+ state.emit(rvc(rv64::C_LW, Tmp2Reg + OffsetXC, Tmp1Reg + OffsetXC));
|
|
|
+ //lw x9, 4(x9)
|
|
|
+ state.emit(rvc(rv64::C_LW, Tmp2Reg + OffsetXC, 16 + Tmp2Reg + OffsetXC));
|
|
|
+ //fcvt.d.w f24, x8
|
|
|
+ state.emit(rvi(rv64::FCVT_D_W, Tmp1RegF, Tmp1Reg));
|
|
|
+ //fcvt.d.w f25, x9
|
|
|
+ state.emit(rvi(rv64::FCVT_D_W, Tmp2RegF, Tmp2Reg));
|
|
|
+ //fadd.d f{dst_lo}, f{dst_lo}, f24
|
|
|
+ state.emit(rvi(rv64::FADD_D, regLoF(isn.dst), regLoF(isn.dst), Tmp1RegF));
|
|
|
+ //fadd.d f{dst_hi}, f{dst_hi}, f25
|
|
|
+ state.emit(rvi(rv64::FADD_D, regHiF(isn.dst), regHiF(isn.dst), Tmp2RegF));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_FSUB_R(HANDLER_ARGS) {
|
|
|
+ isn.dst %= RegisterCountFlt;
|
|
|
+ isn.src %= RegisterCountFlt;
|
|
|
+ //fsub.d f{dst_lo}, f{dst_lo}, f{src_lo}
|
|
|
+ state.emit(rvi(rv64::FSUB_D, regLoF(isn.dst), regLoF(isn.dst), regLoA(isn.src)));
|
|
|
+ //fsub.d f{dst_hi}, f{dst_hi}, f{src_hi}
|
|
|
+ state.emit(rvi(rv64::FSUB_D, regHiF(isn.dst), regHiF(isn.dst), regHiA(isn.src)));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_FSUB_M(HANDLER_ARGS) {
|
|
|
+ isn.dst %= RegisterCountFlt;
|
|
|
+ //x9 = mem
|
|
|
+ genAddressReg(state, isn);
|
|
|
+ //c.lw x8, 0(x9)
|
|
|
+ state.emit(rvc(rv64::C_LW, Tmp2Reg + OffsetXC, Tmp1Reg + OffsetXC));
|
|
|
+ //c.lw x9, 4(x9)
|
|
|
+ state.emit(rvc(rv64::C_LW, Tmp2Reg + OffsetXC, 16 + Tmp2Reg + OffsetXC));
|
|
|
+ //fcvt.d.w f24, x8
|
|
|
+ state.emit(rvi(rv64::FCVT_D_W, Tmp1RegF, Tmp1Reg));
|
|
|
+ //fcvt.d.w f25, x9
|
|
|
+ state.emit(rvi(rv64::FCVT_D_W, Tmp2RegF, Tmp2Reg));
|
|
|
+ //fsub.d f{dst_lo}, f{dst_lo}, f24
|
|
|
+ state.emit(rvi(rv64::FSUB_D, regLoF(isn.dst), regLoF(isn.dst), Tmp1RegF));
|
|
|
+ //fsub.d f{dst_hi}, f{dst_hi}, f25
|
|
|
+ state.emit(rvi(rv64::FSUB_D, regHiF(isn.dst), regHiF(isn.dst), Tmp2RegF));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_FSCAL_R(HANDLER_ARGS) {
|
|
|
+ isn.dst %= RegisterCountFlt;
|
|
|
+ //fmv.x.d x8, f{dst_lo}
|
|
|
+ state.emit(rvi(rv64::FMV_X_D, Tmp1Reg, regLoF(isn.dst)));
|
|
|
+ //fmv.x.d x9, f{dst_hi}
|
|
|
+ state.emit(rvi(rv64::FMV_X_D, Tmp2Reg, regHiF(isn.dst)));
|
|
|
+ //c.xor x8, x12
|
|
|
+ state.emit(rvc(rv64::C_XOR, Tmp1Reg + OffsetXC, MaskFscalReg + OffsetXC));
|
|
|
+ //c.xor x9, x12
|
|
|
+ state.emit(rvc(rv64::C_XOR, Tmp2Reg + OffsetXC, MaskFscalReg + OffsetXC));
|
|
|
+ //fmv.d.x f{dst_lo}, x8
|
|
|
+ state.emit(rvi(rv64::FMV_D_X, regLoF(isn.dst), Tmp1Reg));
|
|
|
+ //fmv.d.x f{dst_hi}, x9
|
|
|
+ state.emit(rvi(rv64::FMV_D_X, regHiF(isn.dst), Tmp2Reg));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_FMUL_R(HANDLER_ARGS) {
|
|
|
+ isn.dst %= RegisterCountFlt;
|
|
|
+ isn.src %= RegisterCountFlt;
|
|
|
+ //fmul.d f{dst_lo}, f{dst_lo}, f{src_lo}
|
|
|
+ state.emit(rvi(rv64::FMUL_D, regLoE(isn.dst), regLoE(isn.dst), regLoA(isn.src)));
|
|
|
+ //fmul.d f{dst_hi}, f{dst_hi}, f{src_hi}
|
|
|
+ state.emit(rvi(rv64::FMUL_D, regHiE(isn.dst), regHiE(isn.dst), regHiA(isn.src)));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_FDIV_M(HANDLER_ARGS) {
|
|
|
+ isn.dst %= RegisterCountFlt;
|
|
|
+ //x9 = mem
|
|
|
+ genAddressReg(state, isn);
|
|
|
+ //lw x8, 0(x9)
|
|
|
+ state.emit(rvc(rv64::C_LW, Tmp2Reg + OffsetXC, Tmp1Reg + OffsetXC));
|
|
|
+ //lw x9, 4(x9)
|
|
|
+ state.emit(rvc(rv64::C_LW, Tmp2Reg + OffsetXC, 16 + Tmp2Reg + OffsetXC));
|
|
|
+ //fcvt.d.w f24, x8
|
|
|
+ state.emit(rvi(rv64::FCVT_D_W, Tmp1RegF, Tmp1Reg));
|
|
|
+ //fcvt.d.w f25, x9
|
|
|
+ state.emit(rvi(rv64::FCVT_D_W, Tmp2RegF, Tmp2Reg));
|
|
|
+ //fmv.x.d x8, f24
|
|
|
+ state.emit(rvi(rv64::FMV_X_D, Tmp1Reg, Tmp1RegF));
|
|
|
+ //fmv.x.d x9, f25
|
|
|
+ state.emit(rvi(rv64::FMV_X_D, Tmp2Reg, Tmp2RegF));
|
|
|
+ //c.and x8, x13
|
|
|
+ state.emit(rvc(rv64::C_AND, Tmp1Reg + OffsetXC, MaskEclear + OffsetXC));
|
|
|
+ //c.and x9, x13
|
|
|
+ state.emit(rvc(rv64::C_AND, Tmp2Reg + OffsetXC, MaskEclear + OffsetXC));
|
|
|
+ //c.or x8, x14
|
|
|
+ state.emit(rvc(rv64::C_OR, Tmp1Reg + OffsetXC, MaskEsetLo + OffsetXC));
|
|
|
+ //c.or x9, x15
|
|
|
+ state.emit(rvc(rv64::C_OR, Tmp2Reg + OffsetXC, MaskEsetHi + OffsetXC));
|
|
|
+ //fmv.d.x f24, x8
|
|
|
+ state.emit(rvi(rv64::FMV_D_X, Tmp1RegF, Tmp1Reg));
|
|
|
+ //fmv.d.x f25, x9
|
|
|
+ state.emit(rvi(rv64::FMV_D_X, Tmp2RegF, Tmp2Reg));
|
|
|
+ //fdiv.d f{dst_lo}, f{dst_lo}, f24
|
|
|
+ state.emit(rvi(rv64::FDIV_D, regLoE(isn.dst), regLoE(isn.dst), Tmp1RegF));
|
|
|
+ //fdiv.d f{dst_hi}, f{dst_hi}, f25
|
|
|
+ state.emit(rvi(rv64::FDIV_D, regHiE(isn.dst), regHiE(isn.dst), Tmp2RegF));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_FSQRT_R(HANDLER_ARGS) {
|
|
|
+ isn.dst %= RegisterCountFlt;
|
|
|
+ //fsqrt.d f{dst_lo}, f{dst_lo}
|
|
|
+ state.emit(rvi(rv64::FSQRT_D, regLoE(isn.dst), regLoE(isn.dst)));
|
|
|
+ //fsqrt.d f{dst_hi}, f{dst_hi}
|
|
|
+ state.emit(rvi(rv64::FSQRT_D, regHiE(isn.dst), regHiE(isn.dst)));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_CBRANCH(HANDLER_ARGS) {
|
|
|
+ int reg = isn.dst;
|
|
|
+ int target = state.registerUsage[reg] + 1;
|
|
|
+ int shift = isn.getModCond() + ConditionOffset;
|
|
|
+ int32_t imm = unsigned32ToSigned2sCompl(isn.getImm32());
|
|
|
+ imm |= (1UL << shift);
|
|
|
+ if (ConditionOffset > 0 || shift > 0)
|
|
|
+ imm &= ~(1UL << (shift - 1));
|
|
|
+ //x8 = branchMask
|
|
|
+ emitImm32(state, (int32_t)ConditionMask << shift, Tmp1Reg);
|
|
|
+ //x{dst} += {imm}
|
|
|
+ emitImm32(state, imm, regR(isn.dst), regR(isn.dst), Tmp2Reg);
|
|
|
+ //and x8, x8, x{dst}
|
|
|
+ state.emit(rvi(rv64::AND, Tmp1Reg, Tmp1Reg, regR(isn.dst)));
|
|
|
+ int32_t targetPos = state.instructionOffsets[target];
|
|
|
+ int offset = targetPos - state.codePos;
|
|
|
+ if (offset >= -256) { //C.BEQZ only has a range of 256B
|
|
|
+ //c.beqz x8, {offset}
|
|
|
+ int imm8 = 1; //sign bit is always 1
|
|
|
+ int imm21 = offset & 6; //offset[2:1]
|
|
|
+ int imm5 = (offset >> 5) & 1; //offset[5]
|
|
|
+ int imm43 = offset & 24; //offset[4:3]
|
|
|
+ int imm76 = (offset >> 3) & 24; //offset[7:6]
|
|
|
+ state.emit(rvc(rv64::C_BEQZ, imm8, imm43 + (Tmp1Reg + OffsetXC), imm76 + imm21 + imm5));
|
|
|
+ }
|
|
|
+ else if (offset >= -4096) { //BEQ only has a range of 4KB
|
|
|
+ //beq x8, x0, offset
|
|
|
+ int imm12 = 1 << 11; //sign bit is always 1
|
|
|
+ int imm105 = offset & 2016; //offset[10:5]
|
|
|
+ int imm41 = offset & 30; //offset[4:1]
|
|
|
+ int imm11 = (offset >> 11) & 1; //offset[11]
|
|
|
+ state.emit(rvi(rv64::BEQ, imm41 + imm11, Tmp1Reg, imm12 + imm105));
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ //c.bnez x8, +6
|
|
|
+ state.emit(rvc(rv64::C_BNEZ, Tmp1Reg + OffsetXC, 6));
|
|
|
+ //j targetPos
|
|
|
+ emitJump(state, 0, state.codePos, targetPos);
|
|
|
+ state.codePos += 4;
|
|
|
+ }
|
|
|
+ //mark all registers as used
|
|
|
+ for (unsigned j = 0; j < RegistersCount; ++j) {
|
|
|
+ state.registerUsage[j] = i;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_CFROUND(HANDLER_ARGS) {
|
|
|
+ int32_t imm = (isn.getImm32() - 2) & 63; //-2 to avoid a later left shift to multiply by 4
|
|
|
+ if (imm != 0) {
|
|
|
+#ifdef __riscv_zbb
|
|
|
+ //rori x8, x{src}, {imm}
|
|
|
+ state.emit(rvi(rv64::RORI, Tmp1Reg, regR(isn.src), imm));
|
|
|
+#else
|
|
|
+ int32_t imml = -imm & 63;
|
|
|
+ //srli x8, x{src}, {imm}
|
|
|
+ state.emit(rvi(rv64::SRLI, Tmp1Reg, regR(isn.src), imm));
|
|
|
+ //slli x9, x{src}, {imml}
|
|
|
+ state.emit(rvi(rv64::SLLI, Tmp2Reg, regR(isn.src), imml));
|
|
|
+ //c.or x8, x9
|
|
|
+ state.emit(rvc(rv64::C_OR, Tmp1Reg + OffsetXC, Tmp2Reg + OffsetXC));
|
|
|
+#endif
|
|
|
+ //c.andi x8, 12
|
|
|
+ state.emit(rvc(rv64::C_ANDI, Tmp1Reg + OffsetXC, 12));
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ //and x8, x{src}, 12
|
|
|
+ state.emit(rvi(rv64::ANDI, Tmp1Reg, regR(isn.src), 12));
|
|
|
+ }
|
|
|
+ //c.add x8, x3
|
|
|
+ state.emit(rvc(rv64::C_ADD, Tmp1Reg, LiteralPoolReg));
|
|
|
+ //c.lw x8, 64(x8)
|
|
|
+ state.emit(rvc(rv64::C_LW, Tmp1Reg + OffsetXC, 8 + Tmp1Reg + OffsetXC));
|
|
|
+ //fsrm x8
|
|
|
+ state.emit(rvi(rv64::FSRM, 0, Tmp1Reg, 0));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_ISTORE(HANDLER_ARGS) {
|
|
|
+ genAddressRegDst(state, isn);
|
|
|
+ //sd x{src}, 0(x9)
|
|
|
+ state.emit(rvi(rv64::SD, 0, Tmp2Reg, regR(isn.src)));
|
|
|
+ }
|
|
|
+
|
|
|
+ static void v1_NOP(HANDLER_ARGS) {
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+#include "instruction_weights.hpp"
|
|
|
+
|
|
|
+namespace {
|
|
|
+
|
|
|
+#define INST_HANDLE1(x) REPN(&randomx::v1_##x, WT(x))
|
|
|
+#define INST_HANDLE2(x) REPN(&randomx::v2_##x, WT(x))
|
|
|
+
|
|
|
+ InstructionHandler* opcodeMap1[256] = {
|
|
|
+ INST_HANDLE1(IADD_RS)
|
|
|
+ INST_HANDLE1(IADD_M)
|
|
|
+ INST_HANDLE1(ISUB_R)
|
|
|
+ INST_HANDLE1(ISUB_M)
|
|
|
+ INST_HANDLE1(IMUL_R)
|
|
|
+ INST_HANDLE1(IMUL_M)
|
|
|
+ INST_HANDLE1(IMULH_R)
|
|
|
+ INST_HANDLE1(IMULH_M)
|
|
|
+ INST_HANDLE1(ISMULH_R)
|
|
|
+ INST_HANDLE1(ISMULH_M)
|
|
|
+ INST_HANDLE1(IMUL_RCP)
|
|
|
+ INST_HANDLE1(INEG_R)
|
|
|
+ INST_HANDLE1(IXOR_R)
|
|
|
+ INST_HANDLE1(IXOR_M)
|
|
|
+ INST_HANDLE1(IROR_R)
|
|
|
+ INST_HANDLE1(IROL_R)
|
|
|
+ INST_HANDLE1(ISWAP_R)
|
|
|
+ INST_HANDLE1(FSWAP_R)
|
|
|
+ INST_HANDLE1(FADD_R)
|
|
|
+ INST_HANDLE1(FADD_M)
|
|
|
+ INST_HANDLE1(FSUB_R)
|
|
|
+ INST_HANDLE1(FSUB_M)
|
|
|
+ INST_HANDLE1(FSCAL_R)
|
|
|
+ INST_HANDLE1(FMUL_R)
|
|
|
+ INST_HANDLE1(FDIV_M)
|
|
|
+ INST_HANDLE1(FSQRT_R)
|
|
|
+ INST_HANDLE1(CBRANCH)
|
|
|
+ INST_HANDLE1(CFROUND)
|
|
|
+ INST_HANDLE1(ISTORE)
|
|
|
+ INST_HANDLE1(NOP)
|
|
|
+ };
|
|
|
+}
|
tevador