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@@ -0,0 +1,645 @@
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+/*
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+Copyright (c) 2018-2019, tevador <tevador@gmail.com>
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+
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+All rights reserved.
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+
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+Redistribution and use in source and binary forms, with or without
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+modification, are permitted provided that the following conditions are met:
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+ * Redistributions of source code must retain the above copyright
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+ notice, this list of conditions and the following disclaimer.
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+ * Redistributions in binary form must reproduce the above copyright
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+ notice, this list of conditions and the following disclaimer in the
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+ documentation and/or other materials provided with the distribution.
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+ * Neither the name of the copyright holder nor the
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+ names of its contributors may be used to endorse or promote products
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+ derived from this software without specific prior written permission.
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+
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+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+*/
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+
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+#include "utility.hpp"
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+#include "../common.hpp"
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+#include "../aes_hash.hpp"
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+#include "../program.hpp"
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+#include "../blake2/blake2.h"
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+#include <algorithm>
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+#include <iomanip>
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+
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+int analyze(randomx::Program& p);
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+int executeInOrder(randomx::Program& p, randomx::Program& original, bool print, int executionPorts, int memoryPorts, bool speculate, int pipeline);
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+int executeOutOfOrder(randomx::Program& p, randomx::Program& original, bool print, int executionPorts, int memoryPorts, bool speculate, int pipeline);
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+
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+constexpr uint32_t DST_NOP = 0;
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+constexpr uint32_t DST_INT = 1;
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+constexpr uint32_t DST_FLT = 2;
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+constexpr uint32_t DST_MEM = 3;
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+constexpr uint32_t MASK_DST = 3;
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+
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+constexpr uint32_t SRC_NOP = 0;
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+constexpr uint32_t SRC_INT = 4;
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+constexpr uint32_t SRC_FLT = 8;
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+constexpr uint32_t SRC_MEM = 12;
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+constexpr uint32_t MASK_SRC = 12;
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+
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+constexpr uint32_t OP_CFROUND = 16;
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+constexpr uint32_t OP_SWAP = 32;
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+constexpr uint32_t OP_BRANCH = 48;
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+constexpr uint32_t MASK_EXT = 48;
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+
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+constexpr uint32_t OP_FLOAT = 64;
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+constexpr uint32_t BRANCH_TARGET = 128;
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+
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+//template<bool softAes>
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+void generate(randomx::Program& p, uint32_t nonce) {
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+ alignas(16) uint64_t hash[8];
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+ blake2b(hash, sizeof(hash), &nonce, sizeof(nonce), nullptr, 0);
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+ fillAes1Rx4<false>((void*)hash, sizeof(p), &p);
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+}
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+
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+bool has(randomx::Instruction& instr, uint32_t mask, uint32_t prop) {
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+ return (instr.opcode & mask) == prop;
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+}
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+
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+bool has(randomx::Instruction& instr, uint32_t prop) {
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+ return (instr.opcode & prop) != 0;
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+}
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+
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+int main(int argc, char** argv) {
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+ int nonces, seed, executionPorts, memoryPorts, pipeline;
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+ bool print, reorder, speculate;
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+ readOption("--print", argc, argv, print);
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+ readOption("--reorder", argc, argv, reorder);
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+ readOption("--speculate", argc, argv, speculate);
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+ readIntOption("--nonces", argc, argv, nonces, 1);
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+ readIntOption("--seed", argc, argv, seed, 0);
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+ readIntOption("--executionPorts", argc, argv, executionPorts, 4);
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+ readIntOption("--memoryPorts", argc, argv, memoryPorts, 2);
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+ readIntOption("--pipeline", argc, argv, pipeline, 3 + speculate);
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+ randomx::Program p, original;
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+ double totalCycles = 0.0;
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+ double jumpCount = 0;
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+ for (int i = 0; i < nonces; ++i) {
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+ generate(original, i ^ seed);
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+ memcpy(&p, &original, sizeof(p));
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+ jumpCount += analyze(p);
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+ totalCycles +=
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+ reorder
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+ ?
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+ executeOutOfOrder(p, original, print, executionPorts, memoryPorts, speculate, pipeline)
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+ :
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+ executeInOrder(p, original, print, executionPorts, memoryPorts, speculate, pipeline);
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+ }
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+ totalCycles /= nonces;
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+ jumpCount /= nonces;
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+ std::cout << "Execution took " << totalCycles << " cycles per program" << std::endl;
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+ //std::cout << "Jump count: " << jumpCount << std::endl;
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+ return 0;
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+}
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+
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+int executeInOrder(randomx::Program& p, randomx::Program& original, bool print, int executionPorts, int memoryPorts, bool speculate, int pipeline) {
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+ int cycle = pipeline - 1;
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+ int index = 0;
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+ int branchCount = 0;
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+ int int_reg_ready[randomx::RegistersCount] = { 0 };
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+ int flt_reg_ready[randomx::RegistersCount] = { 0 };
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+ //each workgroup takes 1 or 2 cycles (2 cycles if any instruction has a memory operand)
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+ while (index < RANDOMX_PROGRAM_SIZE) {
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+ int memoryReads = 0;
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+ int memoryAccesses = 0;
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+ bool hasRound = false;
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+ int workers = 0;
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+ //std::cout << "-----------" << std::endl;
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+ for (; workers < executionPorts && memoryAccesses < memoryPorts && index < RANDOMX_PROGRAM_SIZE; ++workers) {
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+ auto& instr = p(index);
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+ auto& origi = original(index);
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+ origi.dst %= randomx::RegistersCount;
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+ origi.src %= randomx::RegistersCount;
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+
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+ //check dependencies
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+ if (has(instr, MASK_SRC, SRC_INT) && int_reg_ready[instr.src] > cycle)
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+ break;
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+
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+ if (has(instr, MASK_SRC, SRC_MEM) && int_reg_ready[instr.src] > cycle)
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+ break;
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+
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+ if (has(instr, MASK_DST, DST_FLT) && flt_reg_ready[instr.dst] > cycle)
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+ break;
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+
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+ if (has(instr, MASK_DST, DST_INT) && int_reg_ready[instr.dst] > cycle)
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+ break;
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+
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+ if (hasRound && has(instr, OP_FLOAT))
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+ break;
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+
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+ //execute
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+ index++;
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+
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+ if (has(instr, MASK_EXT, OP_BRANCH)) {
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+ branchCount++;
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+ }
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+
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+ if (has(instr, MASK_DST, DST_FLT))
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+ flt_reg_ready[instr.dst] = cycle + 1;
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+
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+ if (has(instr, MASK_DST, DST_INT))
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+ int_reg_ready[instr.dst] = cycle + 1;
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+
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+ if (has(instr, MASK_EXT, OP_SWAP)) {
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+ int_reg_ready[instr.src] = cycle + 1;
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+ }
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+
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+ if (has(instr, MASK_EXT, OP_CFROUND))
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+ hasRound = true;
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+
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+ if (has(instr, MASK_SRC, SRC_MEM)) {
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+ memoryReads++;
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+ memoryAccesses++;
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+ if (print)
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+ std::cout << std::setw(2) << (cycle + 2) << ": " << origi;
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+ }
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+ else {
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+ if (print)
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+ std::cout << std::setw(2) << (cycle + 1) << ": " << origi;
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+ }
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+
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+ if (has(instr, MASK_DST, DST_MEM)) {
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+ memoryAccesses++;
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+ }
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+
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+ //non-speculative execution must stall after branch
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+ if (!speculate && has(instr, MASK_EXT, OP_BRANCH)) {
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+ cycle += pipeline - 1;
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+ break;
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+ }
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+ }
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+ //std::cout << " workers: " << workers << std::endl;
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+ cycle++;
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+ if (memoryReads)
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+ cycle++;
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+ }
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+ if (speculate) {
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+ //account for mispredicted branches
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+ int i = 0;
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+ while (branchCount--) {
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+ auto entropy = p.getEntropy(i / 8);
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+ entropy >> (i % 8) * 8;
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+ if ((entropy & 0xff) == 0) // 1/256 chance to flush the pipeline
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+ cycle += pipeline - 1;
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+ }
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+ }
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+ return cycle;
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+}
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+
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+int executeOutOfOrder(randomx::Program& p, randomx::Program& original, bool print, int executionPorts, int memoryPorts, bool speculate, int pipeline) {
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+ int index = 0;
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+ int busyExecutionPorts[RANDOMX_PROGRAM_SIZE] = { 0 };
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+ int busyMemoryPorts[RANDOMX_PROGRAM_SIZE] = { 0 };
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+ int int_reg_ready[randomx::RegistersCount] = { 0 };
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+ int flt_reg_ready[randomx::RegistersCount] = { 0 };
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+ int fprcReady = 0;
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+ int lastBranch = 0;
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+ int branchCount = 0;
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+ for (; index < RANDOMX_PROGRAM_SIZE; ++index) {
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+ auto& instr = p(index);
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+ int retireCycle = pipeline - 1;
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+
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+ //non-speculative execution cannot reorder across branches
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+ if (!speculate && !has(instr, MASK_EXT, OP_BRANCH))
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+ retireCycle = std::max(lastBranch + pipeline - 1, retireCycle);
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+
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+ //check dependencies
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+ if (has(instr, MASK_SRC, SRC_INT)) {
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+ retireCycle = std::max(retireCycle, int_reg_ready[instr.src]);
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+ }
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+
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+ if (has(instr, MASK_SRC, SRC_MEM)) {
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+ retireCycle = std::max(retireCycle, int_reg_ready[instr.src]);
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+ //find free memory port
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+ do {
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+ retireCycle++;
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+ } while (busyMemoryPorts[retireCycle - 1] >= memoryPorts);
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+ busyMemoryPorts[retireCycle - 1]++;
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+ }
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+
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+ if (has(instr, MASK_DST, DST_FLT)) {
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+ retireCycle = std::max(retireCycle, flt_reg_ready[instr.dst]);
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+ }
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+
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+ if (has(instr, MASK_DST, DST_INT)) {
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+ retireCycle = std::max(retireCycle, int_reg_ready[instr.dst]);
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+ }
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+
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+ //floating point operations depend on the fprc register
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+ if (has(instr, OP_FLOAT))
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+ retireCycle = std::max(retireCycle, fprcReady);
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+
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+ //execute
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+ if (has(instr, MASK_DST, DST_MEM)) {
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+ //find free memory port
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+ do {
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+ retireCycle++;
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+ } while (busyMemoryPorts[retireCycle - 1] >= memoryPorts);
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+ busyMemoryPorts[retireCycle - 1]++;
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+ }
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+
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+ if (has(instr, MASK_DST, DST_FLT)) {
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+ //find free execution port
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+ do {
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+ retireCycle++;
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+ } while (busyExecutionPorts[retireCycle - 1] >= executionPorts);
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+ busyExecutionPorts[retireCycle - 1]++;
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+ flt_reg_ready[instr.dst] = retireCycle;
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+ }
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+
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+ if (has(instr, MASK_DST, DST_INT)) {
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+ //find free execution port
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+ do {
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+ retireCycle++;
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+ } while (busyExecutionPorts[retireCycle - 1] >= executionPorts);
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+ busyExecutionPorts[retireCycle - 1]++;
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+ int_reg_ready[instr.dst] = retireCycle;
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+ }
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+
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+ if (has(instr, MASK_EXT, OP_SWAP)) {
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+ int_reg_ready[instr.src] = retireCycle;
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+ }
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+
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+ if (has(instr, MASK_EXT, OP_CFROUND)) {
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+ do {
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+ retireCycle++;
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+ } while (busyExecutionPorts[retireCycle - 1] >= executionPorts);
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+ busyExecutionPorts[retireCycle - 1]++;
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+ fprcReady = retireCycle;
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+ }
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+
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+ if (has(instr, MASK_EXT, OP_BRANCH)) {
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+ /*if (!speculate && instr.mod == 1) { //simulated predication
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+ do {
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+ retireCycle++;
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+ } while (busyExecutionPorts[retireCycle - 1] >= executionPorts);
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+ busyExecutionPorts[retireCycle - 1]++;
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+ int_reg_ready[instr.dst] = retireCycle;
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+ }*/
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+ //else {
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+ lastBranch = std::max(lastBranch, retireCycle);
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+ branchCount++;
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+ //}
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+ }
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+
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+ //print
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+ auto& origi = original(index);
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+ origi.dst %= randomx::RegistersCount;
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+ origi.src %= randomx::RegistersCount;
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+ if (print) {
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+ std::cout << std::setw(2) << retireCycle << ": " << origi;
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+ if (has(instr, MASK_EXT, OP_BRANCH)) {
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+ std::cout << " jump: " << (int)instr.mod << std::endl;
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+ }
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+ }
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+ }
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+ int cycle = 0;
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+ for (int i = 0; i < randomx::RegistersCount; ++i) {
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+ cycle = std::max(cycle, int_reg_ready[i]);
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+ }
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+ for (int i = 0; i < randomx::RegistersCount; ++i) {
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+ cycle = std::max(cycle, flt_reg_ready[i]);
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+ }
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+ if (speculate) {
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+ //account for mispredicted branches
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+ int i = 0;
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+ while (branchCount--) {
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+ auto entropy = p.getEntropy(i / 8);
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+ entropy >> (i % 8) * 8;
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+ if ((entropy & 0xff) == 0) // 1/256 chance to flush the pipeline
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+ cycle += pipeline - 1;
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+ }
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+ }
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+ return cycle;
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+}
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+
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+#include "../instruction_weights.hpp"
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+
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+//old register selection
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+struct RegisterUsage {
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+ int32_t lastUsed;
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+ int32_t count;
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+};
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+
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+inline int getConditionRegister(RegisterUsage(®isterUsage)[randomx::RegistersCount]) {
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+ int min = INT_MAX;
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+ int minCount = 0;
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+ int minIndex;
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+ //prefer registers that have been used as a condition register fewer times
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+ for (unsigned i = 0; i < randomx::RegistersCount; ++i) {
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+ if (registerUsage[i].lastUsed < min || (registerUsage[i].lastUsed == min && registerUsage[i].count < minCount)) {
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+ min = registerUsage[i].lastUsed;
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+ minCount = registerUsage[i].count;
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+ minIndex = i;
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+ }
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+ }
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+ return minIndex;
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+}
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+
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+int analyze(randomx::Program& p) {
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+ int jumpCount = 0;
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+ RegisterUsage registerUsage[randomx::RegistersCount];
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+ for (unsigned i = 0; i < randomx::RegistersCount; ++i) {
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+ registerUsage[i].lastUsed = -1;
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+ registerUsage[i].count = 0;
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+ }
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+ for (unsigned i = 0; i < RANDOMX_PROGRAM_SIZE; ++i) {
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+ auto& instr = p(i);
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+ int opcode = instr.opcode;
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+ instr.opcode = 0;
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+ switch (opcode) {
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+ CASE_REP(IADD_RS) {
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+ instr.dst = instr.dst % randomx::RegistersCount;
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+ instr.src = instr.src % randomx::RegistersCount;
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+ instr.opcode |= SRC_INT;
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+ instr.opcode |= DST_INT;
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+ registerUsage[instr.dst].lastUsed = i;
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+ } break;
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+
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+ CASE_REP(IADD_M) {
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+ instr.dst = instr.dst % randomx::RegistersCount;
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+ instr.src = instr.src % randomx::RegistersCount;
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+ instr.opcode |= SRC_MEM;
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+ instr.opcode |= DST_INT;
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+ if (instr.src != instr.dst) {
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+ instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask);
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+ }
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|
|
+ else {
|
|
|
+ instr.imm32 &= randomx::ScratchpadL3Mask;
|
|
|
+ }
|
|
|
+ registerUsage[instr.dst].lastUsed = i;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(ISUB_R) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= DST_INT;
|
|
|
+ instr.opcode |= SRC_INT;
|
|
|
+ registerUsage[instr.dst].lastUsed = i;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(ISUB_M) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= SRC_MEM;
|
|
|
+ instr.opcode |= DST_INT;
|
|
|
+ if (instr.src != instr.dst) {
|
|
|
+ instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask);
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ instr.imm32 &= randomx::ScratchpadL3Mask;
|
|
|
+ }
|
|
|
+ registerUsage[instr.dst].lastUsed = i;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(IMUL_R) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= DST_INT;
|
|
|
+ instr.opcode |= SRC_INT;
|
|
|
+ registerUsage[instr.dst].lastUsed = i;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(IMUL_M) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= SRC_MEM;
|
|
|
+ instr.opcode |= DST_INT;
|
|
|
+ if (instr.src != instr.dst) {
|
|
|
+ instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask);
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ instr.imm32 &= randomx::ScratchpadL3Mask;
|
|
|
+ }
|
|
|
+ registerUsage[instr.dst].lastUsed = i;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(IMULH_R) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= DST_INT;
|
|
|
+ instr.opcode |= SRC_INT;
|
|
|
+ registerUsage[instr.dst].lastUsed = i;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(IMULH_M) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= SRC_MEM;
|
|
|
+ instr.opcode |= DST_INT;
|
|
|
+ if (instr.src != instr.dst) {
|
|
|
+ instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask);
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ instr.imm32 &= randomx::ScratchpadL3Mask;
|
|
|
+ }
|
|
|
+ registerUsage[instr.dst].lastUsed = i;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(ISMULH_R) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= DST_INT;
|
|
|
+ instr.opcode |= SRC_INT;
|
|
|
+ registerUsage[instr.dst].lastUsed = i;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(ISMULH_M) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= SRC_MEM;
|
|
|
+ instr.opcode |= DST_INT;
|
|
|
+ if (instr.src != instr.dst) {
|
|
|
+ instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask);
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ instr.imm32 &= randomx::ScratchpadL3Mask;
|
|
|
+ }
|
|
|
+ registerUsage[instr.dst].lastUsed = i;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(IMUL_RCP) {
|
|
|
+ uint64_t divisor = instr.getImm32();
|
|
|
+ if (!randomx::isPowerOf2(divisor)) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.opcode |= DST_INT;
|
|
|
+ registerUsage[instr.dst].lastUsed = i;
|
|
|
+ }
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(INEG_R) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.opcode |= DST_INT;
|
|
|
+ registerUsage[instr.dst].lastUsed = i;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(IXOR_R) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= DST_INT;
|
|
|
+ instr.opcode |= SRC_INT;
|
|
|
+ registerUsage[instr.dst].lastUsed = i;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(IXOR_M) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= SRC_MEM;
|
|
|
+ instr.opcode |= DST_INT;
|
|
|
+ if (instr.src != instr.dst) {
|
|
|
+ instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask);
|
|
|
+ }
|
|
|
+ else {
|
|
|
+ instr.imm32 &= randomx::ScratchpadL3Mask;
|
|
|
+ }
|
|
|
+ registerUsage[instr.dst].lastUsed = i;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(IROR_R) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= DST_INT;
|
|
|
+ instr.opcode |= SRC_INT;
|
|
|
+ registerUsage[instr.dst].lastUsed = i;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(IROL_R) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= DST_INT;
|
|
|
+ instr.opcode |= SRC_INT;
|
|
|
+ registerUsage[instr.dst].lastUsed = i;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(ISWAP_R) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ if (instr.src != instr.dst) {
|
|
|
+ instr.opcode |= DST_INT;
|
|
|
+ instr.opcode |= SRC_INT;
|
|
|
+ instr.opcode |= OP_SWAP;
|
|
|
+ registerUsage[instr.dst].lastUsed = i;
|
|
|
+ registerUsage[instr.src].lastUsed = i;
|
|
|
+ }
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(FSWAP_R) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.opcode |= DST_FLT;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(FADD_R) {
|
|
|
+ instr.dst = instr.dst % randomx::RegisterCountFlt;
|
|
|
+ instr.opcode |= DST_FLT;
|
|
|
+ instr.opcode |= OP_FLOAT;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(FADD_M) {
|
|
|
+ instr.dst = instr.dst % randomx::RegisterCountFlt;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= DST_FLT;
|
|
|
+ instr.opcode |= SRC_MEM;
|
|
|
+ instr.opcode |= OP_FLOAT;
|
|
|
+ instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask);
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(FSUB_R) {
|
|
|
+ instr.dst = instr.dst % randomx::RegisterCountFlt;
|
|
|
+ instr.opcode |= DST_FLT;
|
|
|
+ instr.opcode |= OP_FLOAT;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(FSUB_M) {
|
|
|
+ instr.dst = instr.dst % randomx::RegisterCountFlt;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= DST_FLT;
|
|
|
+ instr.opcode |= SRC_MEM;
|
|
|
+ instr.opcode |= OP_FLOAT;
|
|
|
+ instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask);
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(FSCAL_R) {
|
|
|
+ instr.dst = instr.dst % randomx::RegisterCountFlt;
|
|
|
+ instr.opcode |= DST_FLT;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(FMUL_R) {
|
|
|
+ instr.dst = 4 + instr.dst % randomx::RegisterCountFlt;
|
|
|
+ instr.opcode |= DST_FLT;
|
|
|
+ instr.opcode |= OP_FLOAT;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(FDIV_M) {
|
|
|
+ instr.dst = 4 + instr.dst % randomx::RegisterCountFlt;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= DST_FLT;
|
|
|
+ instr.opcode |= SRC_MEM;
|
|
|
+ instr.opcode |= OP_FLOAT;
|
|
|
+ instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask);
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(FSQRT_R) {
|
|
|
+ instr.dst = 4 + instr.dst % randomx::RegisterCountFlt;
|
|
|
+ instr.opcode |= DST_FLT;
|
|
|
+ instr.opcode |= OP_FLOAT;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(CBRANCH) {
|
|
|
+ instr.opcode |= OP_BRANCH;
|
|
|
+ instr.opcode |= DST_INT;
|
|
|
+ //jump condition
|
|
|
+ //int reg = getConditionRegister(registerUsage);
|
|
|
+ int reg = instr.dst % randomx::RegistersCount;
|
|
|
+ int target = registerUsage[reg].lastUsed;
|
|
|
+ int offset = (i - target);
|
|
|
+ instr.mod = offset;
|
|
|
+ jumpCount += offset;
|
|
|
+ p(target + 1).opcode |= BRANCH_TARGET;
|
|
|
+ registerUsage[reg].count++;
|
|
|
+ instr.dst = reg;
|
|
|
+ //mark all registers as used
|
|
|
+ for (unsigned j = 0; j < randomx::RegistersCount; ++j) {
|
|
|
+ registerUsage[j].lastUsed = i;
|
|
|
+ }
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(CFROUND) {
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= SRC_INT;
|
|
|
+ instr.opcode |= OP_CFROUND;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(ISTORE) {
|
|
|
+ instr.dst = instr.dst % randomx::RegistersCount;
|
|
|
+ instr.src = instr.src % randomx::RegistersCount;
|
|
|
+ instr.opcode |= SRC_INT;
|
|
|
+ instr.opcode |= DST_MEM;
|
|
|
+ if (instr.getModCond() < randomx::StoreL3Condition)
|
|
|
+ instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask);
|
|
|
+ else
|
|
|
+ instr.imm32 &= randomx::ScratchpadL3Mask;
|
|
|
+ } break;
|
|
|
+
|
|
|
+ CASE_REP(NOP) {
|
|
|
+
|
|
|
+ } break;
|
|
|
+
|
|
|
+ default:
|
|
|
+ UNREACHABLE;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ return jumpCount;
|
|
|
+}
|
tevador