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@@ -26,6 +26,7 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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#include <algorithm>
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#include <stdexcept>
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#include <iomanip>
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+#include "LightProgramGenerator.hpp"
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namespace RandomX {
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// Intel Ivy Bridge reference
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@@ -47,8 +48,8 @@ namespace RandomX {
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}
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namespace LightInstructionOpcode {
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- constexpr int IADD_R = 0;
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- constexpr int IADD_RC = RANDOMX_FREQ_IADD_R + RANDOMX_FREQ_IADD_M;
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+ constexpr int IADD_RS = 0;
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+ constexpr int IADD_RC = RANDOMX_FREQ_IADD_RS + RANDOMX_FREQ_IADD_M;
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constexpr int ISUB_R = IADD_RC + RANDOMX_FREQ_IADD_RC;
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constexpr int IMUL_9C = ISUB_R + RANDOMX_FREQ_ISUB_R + RANDOMX_FREQ_ISUB_M;
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constexpr int IMUL_R = IMUL_9C + RANDOMX_FREQ_IMUL_9C;
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@@ -65,20 +66,18 @@ namespace RandomX {
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}
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const int lightInstructionOpcode[] = {
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- LightInstructionOpcode::IADD_R,
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- LightInstructionOpcode::IADD_R,
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- LightInstructionOpcode::IADD_RC,
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- LightInstructionOpcode::ISUB_R,
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- LightInstructionOpcode::IMUL_9C,
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- LightInstructionOpcode::IMUL_R,
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- LightInstructionOpcode::IMUL_R,
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+ LightInstructionOpcode::IADD_RS,
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+ LightInstructionOpcode::ISUB_R, //ISUB_R
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+ LightInstructionOpcode::ISUB_R, //ISUB_R
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+ LightInstructionOpcode::IMUL_R, //IMUL_R
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+ LightInstructionOpcode::IMUL_R, //IMUL_C
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LightInstructionOpcode::IMULH_R,
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LightInstructionOpcode::ISMULH_R,
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LightInstructionOpcode::IMUL_RCP,
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- LightInstructionOpcode::IXOR_R,
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- LightInstructionOpcode::IXOR_R,
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- LightInstructionOpcode::IROR_R,
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- LightInstructionOpcode::IROR_R,
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+ LightInstructionOpcode::IXOR_R, //IXOR_R
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+ LightInstructionOpcode::IXOR_R, //IXOR_C
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+ LightInstructionOpcode::IROR_R, //IROR_R
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+ LightInstructionOpcode::IROR_R, //IROR_C
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LightInstructionOpcode::COND_R
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};
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@@ -93,37 +92,30 @@ namespace RandomX {
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constexpr type P015 = 6;
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}
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- class Blake2Generator {
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- public:
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- Blake2Generator(const void* seed, int nonce) : dataIndex(sizeof(data)) {
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- memset(data, 0, sizeof(data));
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- memcpy(data, seed, SeedSize);
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- store32(&data[60], nonce);
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- }
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-
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- uint8_t getByte() {
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- checkData(1);
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- return data[dataIndex++];
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- }
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+ Blake2Generator::Blake2Generator(const void* seed, int nonce) : dataIndex(sizeof(data)) {
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+ memset(data, 0, sizeof(data));
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+ memcpy(data, seed, SeedSize);
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+ store32(&data[60], nonce);
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+ }
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- uint32_t getInt32() {
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- checkData(4);
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- auto ret = load32(&data[dataIndex]);
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- dataIndex += 4;
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- return ret;
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- }
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+ uint8_t Blake2Generator::getByte() {
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+ checkData(1);
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+ return data[dataIndex++];
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+ }
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- private:
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- uint8_t data[64];
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- size_t dataIndex;
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+ uint32_t Blake2Generator::getInt32() {
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+ checkData(4);
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+ auto ret = load32(&data[dataIndex]);
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+ dataIndex += 4;
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+ return ret;
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+ }
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- void checkData(const size_t bytesNeeded) {
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- if (dataIndex + bytesNeeded > sizeof(data)) {
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- blake2b(data, sizeof(data), data, sizeof(data), nullptr, 0);
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- dataIndex = 0;
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- }
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+ void Blake2Generator::checkData(const size_t bytesNeeded) {
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+ if (dataIndex + bytesNeeded > sizeof(data)) {
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+ blake2b(data, sizeof(data), data, sizeof(data), nullptr, 0);
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+ dataIndex = 0;
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}
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- };
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+ }
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class RegisterInfo {
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public:
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@@ -201,7 +193,7 @@ namespace RandomX {
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static const MacroOp Xor_ri;
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static const MacroOp Ror_rcl;
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static const MacroOp Ror_ri;
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- static const MacroOp TestJmp_fused;
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+ static const MacroOp TestJz_fused;
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static const MacroOp Xor_self;
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static const MacroOp Cmp_ri;
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static const MacroOp Setcc_r;
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@@ -235,13 +227,13 @@ namespace RandomX {
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const MacroOp MacroOp::Xor_self = MacroOp("xor rcx,rcx", 3);
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const MacroOp MacroOp::Cmp_ri = MacroOp("cmp r,i", 7, 1, ExecutionPort::P015);
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const MacroOp MacroOp::Setcc_r = MacroOp("setcc cl", 3, 1, ExecutionPort::P05);
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- const MacroOp MacroOp::TestJmp_fused = MacroOp("testjz r,i", 13, 0, ExecutionPort::P5);
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+ const MacroOp MacroOp::TestJz_fused = MacroOp("testjz r,i", 13, 0, ExecutionPort::P5);
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const MacroOp IMULH_R_ops_array[] = { MacroOp::Mov_rr, MacroOp::Mul_r, MacroOp::Mov_rr };
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const MacroOp ISMULH_R_ops_array[] = { MacroOp::Mov_rr, MacroOp::Imul_r, MacroOp::Mov_rr };
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const MacroOp IMUL_RCP_ops_array[] = { MacroOp::Mov_ri64, MacroOp(MacroOp::Imul_rr, true) };
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const MacroOp IROR_R_ops_array[] = { MacroOp::Mov_rr, MacroOp::Ror_rcl };
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- const MacroOp COND_R_ops_array[] = { MacroOp::Add_ri, MacroOp(MacroOp::TestJmp_fused, true), MacroOp::Xor_self, MacroOp::Cmp_ri, MacroOp(MacroOp::Setcc_r, true), MacroOp(MacroOp::Add_rr, true) };
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+ const MacroOp COND_R_ops_array[] = { MacroOp::Add_ri, MacroOp(MacroOp::TestJz_fused, true), MacroOp::Xor_self, MacroOp::Cmp_ri, MacroOp(MacroOp::Setcc_r, true), MacroOp(MacroOp::Add_rr, true) };
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class LightInstructionInfo {
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@@ -349,7 +341,7 @@ namespace RandomX {
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class DecoderBuffer {
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public:
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- static DecoderBuffer Default;
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+ static const DecoderBuffer Default;
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template <size_t N>
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DecoderBuffer(const char* name, int index, const int(&arr)[N])
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: name_(name), index_(index), counts_(arr), opsCount_(N) {}
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@@ -365,17 +357,17 @@ namespace RandomX {
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const char* getName() const {
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return name_;
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}
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- const DecoderBuffer& fetchNext(int prevType, Blake2Generator& gen) {
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+ const DecoderBuffer* fetchNext(int prevType, Blake2Generator& gen) const {
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if (prevType == LightInstructionType::IMULH_R || prevType == LightInstructionType::ISMULH_R)
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- return decodeBuffer3310; //2-1-1 decode
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+ return &decodeBuffer3310; //2-1-1 decode
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if (index_ == 0) {
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- return decodeBuffer4444; //IMUL_RCP end
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- }
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- if (index_ == 2) {
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- return decodeBuffer133; //COND_R middle
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+ return &decodeBuffer4444; //IMUL_RCP end
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}
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+ /*if (index_ == 2) {
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+ return &decodeBuffer133; //COND_R middle
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+ }*/
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if (index_ == 7) {
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- return decodeBuffer7333; //COND_R end
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+ return &decodeBuffer7333; //COND_R end
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}
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return fetchNextDefault(gen);
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}
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@@ -393,12 +385,12 @@ namespace RandomX {
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static const DecoderBuffer decodeBuffer3373;
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static const DecoderBuffer decodeBuffer133;
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static const DecoderBuffer* decodeBuffers[7];
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- const DecoderBuffer& fetchNextDefault(Blake2Generator& gen) {
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+ const DecoderBuffer* fetchNextDefault(Blake2Generator& gen) const {
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int select;
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do {
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select = gen.getByte() & 7;
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} while (select == 7);
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- return *decodeBuffers[select];
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+ return decodeBuffers[select];
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}
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};
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@@ -420,7 +412,7 @@ namespace RandomX {
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&DecoderBuffer::decodeBuffer3373,
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};
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- DecoderBuffer DecoderBuffer::Default = DecoderBuffer();
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+ const DecoderBuffer DecoderBuffer::Default = DecoderBuffer();
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const LightInstructionInfo* slot_3[] = { &LightInstructionInfo::ISUB_R, &LightInstructionInfo::IXOR_R };
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const LightInstructionInfo* slot_3L[] = { &LightInstructionInfo::ISUB_R, &LightInstructionInfo::IXOR_R, &LightInstructionInfo::IMULH_R, &LightInstructionInfo::ISMULH_R };
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@@ -472,7 +464,7 @@ namespace RandomX {
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case 4:
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return create(slot_4[gen.getByte() & 3], gen);
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case 7:
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- if (isLast) {
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+ if (false && isLast) {
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return create(slot_7L, gen);
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}
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else {
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@@ -595,7 +587,7 @@ namespace RandomX {
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bool selectDestination(int cycle, RegisterInfo (®isters)[8], Blake2Generator& gen) {
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std::vector<int> availableRegisters;
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for (unsigned i = 0; i < 8; ++i) {
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- if (registers[i].latency <= cycle && (canReuse_ || i != src_) && (registers[i].lastOpGroup != opGroup_ || registers[i].lastOpPar != opGroupPar_))
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+ if (registers[i].latency <= cycle && (canReuse_ || i != src_) && (registers[i].lastOpGroup != opGroup_ || registers[i].lastOpPar != opGroupPar_) && (info_.getType() != LightInstructionType::IADD_RS || i != 5))
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availableRegisters.push_back(i);
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}
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return selectRegister(availableRegisters, gen, dst_);
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@@ -607,6 +599,12 @@ namespace RandomX {
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if (registers[i].latency <= cycle)
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availableRegisters.push_back(i);
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}
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+ if (availableRegisters.size() == 2 && info_.getType() == LightInstructionType::IADD_RS) {
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+ if (availableRegisters[0] == 5 || availableRegisters[1] == 5) {
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+ opGroupPar_ = src_ = 5;
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+ return true;
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+ }
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+ }
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if (selectRegister(availableRegisters, gen, src_)) {
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if (groupParIsSource_)
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opGroupPar_ = src_;
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@@ -666,7 +664,7 @@ namespace RandomX {
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constexpr int V4_SRC_INDEX_BITS = 3;
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constexpr int V4_DST_INDEX_BITS = 3;
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constexpr int CYCLE_MAP_SIZE = RANDOMX_LPROG_LATENCY + 3;
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- constexpr bool TRACE = true;
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+ constexpr bool TRACE = false;
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static int blakeCounter = 0;
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@@ -782,15 +780,14 @@ namespace RandomX {
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}
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}
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- void generateLightProg2(LightProgram& prog, const void* seed, int indexRegister, int nonce) {
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+ double generateLightProg2(LightProgram& prog, Blake2Generator& gen) {
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ExecutionPort::type portBusy[CYCLE_MAP_SIZE][3];
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memset(portBusy, 0, sizeof(portBusy));
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RegisterInfo registers[8];
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- Blake2Generator gen(seed, nonce);
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std::vector<LightInstruction> instructions;
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- DecoderBuffer& fetchLine = DecoderBuffer::Default;
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+ const DecoderBuffer* fetchLine = &DecoderBuffer::Default;
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LightInstruction currentInstruction = LightInstruction::Null;
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int instrIndex = 0;
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int codeSize = 0;
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@@ -806,24 +803,24 @@ namespace RandomX {
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constexpr int MAX_ATTEMPTS = 4;
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while(!portsSaturated) {
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- fetchLine = fetchLine.fetchNext(currentInstruction.getType(), gen);
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- if (TRACE) std::cout << "; ------------- fetch cycle " << cycle << " (" << fetchLine.getName() << ")" << std::endl;
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+ fetchLine = fetchLine->fetchNext(currentInstruction.getType(), gen);
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+ if (TRACE) std::cout << "; ------------- fetch cycle " << cycle << " (" << fetchLine->getName() << ")" << std::endl;
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mopIndex = 0;
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- while (mopIndex < fetchLine.getSize()) {
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+ while (mopIndex < fetchLine->getSize()) {
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int topCycle = cycle;
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if (instrIndex >= currentInstruction.getInfo().getSize()) {
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if (portsSaturated)
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break;
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- currentInstruction = LightInstruction::createForSlot(gen, fetchLine.getCounts()[mopIndex], fetchLine.getSize() == mopIndex + 1, fetchLine.getIndex() == 0 && mopIndex == 0);
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+ currentInstruction = LightInstruction::createForSlot(gen, fetchLine->getCounts()[mopIndex], fetchLine->getSize() == mopIndex + 1, fetchLine->getIndex() == 0 && mopIndex == 0);
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instrIndex = 0;
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if (TRACE) std::cout << "; " << currentInstruction.getInfo().getName() << std::endl;
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}
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MacroOp& mop = currentInstruction.getInfo().getOp(instrIndex);
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- if (fetchLine.getCounts()[mopIndex] != mop.getSize()) {
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- if (TRACE) std::cout << "ERROR instruction " << mop.getName() << " doesn't fit into slot of size " << fetchLine.getCounts()[mopIndex] << std::endl;
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- return;
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+ if (fetchLine->getCounts()[mopIndex] != mop.getSize()) {
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+ if (TRACE) std::cout << "ERROR instruction " << mop.getName() << " doesn't fit into slot of size " << fetchLine->getCounts()[mopIndex] << std::endl;
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+ return DBL_MIN;
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}
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if (TRACE) std::cout << mop.getName() << " ";
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@@ -831,7 +828,7 @@ namespace RandomX {
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mop.setCycle(scheduleCycle);
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if (scheduleCycle < 0) {
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if (TRACE) std::cout << "; Failed at cycle " << cycle << std::endl;
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- return;
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+ return DBL_MIN;
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}
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if (instrIndex == currentInstruction.getInfo().getSrcOp()) {
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@@ -893,25 +890,29 @@ namespace RandomX {
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std::cout << "; (* = in use, _ = idle)" << std::endl;
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int portCycles = 0;
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- for (int i = 0; i < CYCLE_MAP_SIZE; ++i) {
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+ /*for (int i = 0; i < CYCLE_MAP_SIZE; ++i) {
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std::cout << "; " << std::setw(3) << i << " ";
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for (int j = 0; j < 3; ++j) {
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std::cout << (portBusy[i][j] ? '*' : '_');
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portCycles += !!portBusy[i][j];
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}
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std::cout << std::endl;
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- }
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+ }*/
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+
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+ double ipc = (macroOpCount / (double)retireCycle);
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std::cout << "; code size " << codeSize << " bytes" << std::endl;
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std::cout << "; x86 macro-ops: " << macroOpCount << std::endl;
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std::cout << "; RandomX instructions: " << outIndex << std::endl;
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std::cout << "; Execution time: " << retireCycle << " cycles" << std::endl;
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- std::cout << "; IPC = " << (macroOpCount / (double)retireCycle) << std::endl;
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+ std::cout << "; IPC = " << ipc << std::endl;
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std::cout << "; Port-cycles: " << portCycles << std::endl;
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+ std::cout << "; Multiplications: " << mulCount << std::endl;
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int asicLatency[8];
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memset(asicLatency, 0, sizeof(asicLatency));
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+
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for (int i = 0; i < outIndex; ++i) {
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Instruction& instr = prog(i);
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int latDst = asicLatency[instr.dst] + 1;
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@@ -919,7 +920,16 @@ namespace RandomX {
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asicLatency[instr.dst] = std::max(latDst, latSrc);
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}
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- std::cout << "; Multiplications: " << mulCount << std::endl;
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+ int asicLatencyFinal = 0;
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+ int addressReg = 0;
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+ for (int i = 0; i < 8; ++i) {
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+ if (asicLatency[i] > asicLatencyFinal) {
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+ asicLatencyFinal = asicLatency[i];
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+ addressReg = i;
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+ }
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+ }
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+
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+ std::cout << "; ASIC latency: " << asicLatencyFinal << std::endl;
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std::cout << "; ASIC latency:" << std::endl;
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for (int i = 0; i < 8; ++i) {
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@@ -931,5 +941,7 @@ namespace RandomX {
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}
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prog.setSize(outIndex);
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+ prog.setAddressRegister(addressReg);
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+ return addressReg;
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}
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}
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tevador