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@@ -507,8 +507,16 @@ namespace RandomX {
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bool selectDestination(int cycle, RegisterInfo (®isters)[8], Blake2Generator& gen) {
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std::vector<int> availableRegisters;
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+ //Conditions for the destination register:
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+ // * value must be ready at the required cycle
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+ // * cannot be the same as the source register unless the instruction allows it
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+ // - this avoids optimizable instructions such as "xor r, r" or "sub r, r"
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+ // * either the last instruction applied to the register or its source must be different than this instruction
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+ // - this avoids optimizable instruction sequences such as "xor r1, r2; xor r1, r2" or "ror r, C1; ror r, C2" or "add r, C1; add r, C2"
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+ // - it also avoids accumulation of trailing zeroes in registers due to excessive multiplication
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+ // * register r5 cannot be the destination of the IADD_RS instruction (limitation of the x86 lea instruction)
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for (unsigned i = 0; i < 8; ++i) {
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- if (registers[i].latency <= cycle && (canReuse_ || i != src_) && (registers[i].lastOpGroup != opGroup_ || registers[i].lastOpPar != opGroupPar_) && (info_->getType() != SuperscalarInstructionType::IADD_RS || i != 5))
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+ if (registers[i].latency <= cycle && (canReuse_ || i != src_) && (registers[i].lastOpGroup != opGroup_ || registers[i].lastOpPar != opGroupPar_) && (info_->getType() != SuperscalarInstructionType::IADD_RS || i != LimitedAddressRegister))
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availableRegisters.push_back(i);
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}
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return selectRegister(availableRegisters, gen, dst_);
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@@ -516,13 +524,15 @@ namespace RandomX {
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bool selectSource(int cycle, RegisterInfo(®isters)[8], Blake2Generator& gen) {
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std::vector<int> availableRegisters;
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+ //all registers that are ready at the cycle
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for (unsigned i = 0; i < 8; ++i) {
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if (registers[i].latency <= cycle)
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availableRegisters.push_back(i);
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}
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+ //if there are only 2 available registers for IADD_RS and one of them is r5, select it as the source because it cannot be the destination
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if (availableRegisters.size() == 2 && info_->getType() == SuperscalarInstructionType::IADD_RS) {
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- if (availableRegisters[0] == 5 || availableRegisters[1] == 5) {
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- opGroupPar_ = src_ = 5;
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+ if (availableRegisters[0] == LimitedAddressRegister || availableRegisters[1] == LimitedAddressRegister) {
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+ opGroupPar_ = src_ = LimitedAddressRegister;
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return true;
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}
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}
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@@ -656,7 +666,7 @@ namespace RandomX {
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return -1;
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}
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- double generateLightProg2(LightProgram& prog, Blake2Generator& gen) {
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+ double generateSuperscalar(LightProgram& prog, Blake2Generator& gen) {
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ExecutionPort::type portBusy[CYCLE_MAP_SIZE][3];
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memset(portBusy, 0, sizeof(portBusy));
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@@ -674,6 +684,7 @@ namespace RandomX {
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int programSize = 0;
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int mulCount = 0;
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int decodeCycle;
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+ int throwAwayCount = 0;
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//decode instructions for RANDOMX_SUPERSCALAR_LATENCY cycles or until an execution port is saturated.
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//Each decode cycle decodes 16 bytes of x86 code.
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@@ -722,12 +733,20 @@ namespace RandomX {
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}
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//if no register was found, throw the instruction away and try another one
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if (forward == LOOK_FORWARD_CYCLES) {
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- macroOpIndex = currentInstruction.getInfo().getSize();
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- if (TRACE) std::cout << "; THROW away " << currentInstruction.getInfo().getName() << std::endl;
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- continue;
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+ if (throwAwayCount < MAX_THROWAWAY_COUNT) {
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+ throwAwayCount++;
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+ macroOpIndex = currentInstruction.getInfo().getSize();
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+ if (TRACE) std::cout << "; THROW away " << currentInstruction.getInfo().getName() << std::endl;
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+ continue;
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+ }
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+ //abort this decode buffer
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+ /*if (TRACE)*/ std::cout << "Aborting at cycle " << cycle << " with decode buffer " << decodeBuffer->getName() << " - source registers not available" << std::endl;
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+ currentInstruction = LightInstruction::Null;
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+ break;
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}
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if (TRACE) std::cout << "; src = r" << currentInstruction.getSource() << std::endl;
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}
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+ throwAwayCount = 0;
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//find a destination register that will be ready when this instruction executes
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if (macroOpIndex == currentInstruction.getInfo().getDstOp()) {
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int forward;
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@@ -737,12 +756,20 @@ namespace RandomX {
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++cycle;
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}
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if (forward == LOOK_FORWARD_CYCLES) { //throw instruction away
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- macroOpIndex = currentInstruction.getInfo().getSize();
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- if (TRACE) std::cout << "; THROW away " << currentInstruction.getInfo().getName() << std::endl;
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- continue;
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+ if (throwAwayCount < MAX_THROWAWAY_COUNT) {
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+ throwAwayCount++;
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+ macroOpIndex = currentInstruction.getInfo().getSize();
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+ if (TRACE) std::cout << "; THROW away " << currentInstruction.getInfo().getName() << std::endl;
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+ continue;
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+ }
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+ //abort this decode buffer
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+ /*if (TRACE)*/ std::cout << "Aborting at cycle " << cycle << " with decode buffer " << decodeBuffer->getName() << " - destination registers not available" << std::endl;
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+ currentInstruction = LightInstruction::Null;
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+ break;
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}
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if (TRACE) std::cout << "; dst = r" << currentInstruction.getDestination() << std::endl;
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}
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+ throwAwayCount = 0;
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//recalculate when the instruction can be scheduled for execution based on operand availability
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scheduleCycle = scheduleMop<true>(mop, portBusy, scheduleCycle, scheduleCycle);
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tevador